MIT Demonstrates 25 nm Gates with Chromeless Phase-Shift Masks
Ruth DeJule, Associate Editor -- Semiconductor International, 6/1/2000
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Numerical Technologies' (San Jose, Calif.) double exposure technique was extended to the chromeless case. Two masks are used, the first a darkfield with chromeless edges defining the 25 nm gates and the second a binary trim mask that patterns the polysilicon interconnects. Fabricated at Photronics (Milpitas, Calif.), the chromeless phase-shift mask was patterned using a single trench dry etch. Since the gates are patterned by phase edge steps in the glass, no minimum CD features are required on the mask. These well-defined, isolated gate features have 25 nm CD corresponding to k1 = 0.06. Good process latitudes were achieved with DOF values of ~0.6 µm and exposure latitude of 7.3%, a potential issue for robust manufacturing process. This process allows for transistor prototyping of 25 nm isolated gates specified by the 1999 ITRS Roadmap for 2014, according to Fritze. •
Multibeam System Offers Direct-Write Solution
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The tremendous expense associated with next-generation lithography masks is motivating the growth in direct-write schemes. Historically, however, direct-write electron beam systems have had low throughput. With single-column multibeam systems, including projection optics such as SCALPEL and PREVAIL and blanked aperture arrays, throughput and resolution are limited by space-charge effects. The obvious way to increase throughput is with simultaneous writing beams, though various approaches have met with heating issues and the need for low-voltage. One scheme being developed by Ion Diagnostics (Santa Clara, Calif.), multibeam electron lithography system (MELS), uses multiple columns each with multiple beams to generate a large number of parallel writing beams (Figure), thus overcoming space-charge interactions, thermal loading and low-voltage constraints.
In MELS, an array of beam-columns can be as large as the wafer, making throughput independent of wafer size; and because the columns distribute the beam current, Coulomb effects are minimized, according to Dr. N. William Parker, president of Ion Diagnostics. For 300 mm wafers, it is designed with 201 columns, each containing 32 beams. Using a cluster tool architecture, MELS comes with single, dual and triple writing module configurations with throughput of 30, 60 and 90 wph, respectively. Microfabricated cold field emitter arrays supply 15 nA per 50 nm beam and 480 nA per column. Though each cathode is servo-regulated for steady current, remaining fast transition noise is minimized by in situ conditioning, differential pumping and multipass writing. MELS is targeted to meet the Roadmap’s 70 nm node and is extendable to 35 nm. •
