ECP Technology Faces Chemical, Dielectric Hurdles
Alexander E. Braun, Senior Editor -- Semiconductor International, 5/1/2000
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At a Glance | | |
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"The issues confronting ECP are integration and electrical reliability," said Robin Cheung, general manager of the Copper Systems and Modules Product Group of Applied Materials (Santa Clara, Calif.). "You must ensure you can fill and process one million vias the same way as the exemplary one on the SEM. Voiding's no longer the problem."
"Copper technology is heading into the real production world," said Gerhard Beenen, vice president and general manager of the Electrofill Products Division at Novellus Systems (Portland, Ore.). "Everyone's at a different stage. IBM's in a strong position after making copper ICs for almost two years and working up to high volumes. Then there's Motorola, and from there it becomes a horse race. Most first-tier semiconductor manufacturers are working to get copper into production, but are either in a pre-pilot situation or in the early stages of pilot production."
"Over the last 18 months, the industry has solved most of the plating problems," declared Mark Thirsk, marketing manager at Shipley (Marlborough, Mass.). "We've evolved chemistries that came from the printed wiring board world and made them work for semiconductor applications."
Dr. David Maloney, product manager at EKC (Hayward, Calif.), does not see serious obstacles for another three years. "A difficulty will be PVD seed deposition on high-aspect-ratio features, and problems associated with CVD issues." Maloney added that the industry would like to be rid of the barrier layer, replacing it with a material with a lower resistivity than that of conventional barrier materials such as tantalum and tantalum nitride. "There hasn't been much done to entirely eliminate the barrier layer, but there are a few promising approaches on paper," he said.
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Concerns and obstacles
"The major concern now is yield, getting an ECP fill system that produces consistent results," said Cheung. "We've introduced an integrated ECP system with bevel clean and anneal, to deliver consistent, CMP-ready films" (Fig. 1). The industry is addressing integration issues like edge cleaning. Because of ECP deposition and the seed layer, film deposits on the wafer's bevel. "Since CMP can't remove copper from the bevel and backside, after a few layers you can get peeling due to film build-up," pointed out Cheung.
Another major attention area is copper anneal. When copper ECP work began, it was discovered that the film is unstable and self-anneals even at room temperature. Each plated wafer heading for CMP could be different, depending on how much time elapsed before it reached the CMP step, a period that can vary depending on load size or tool selection. This can cause widespread electromigration distribution due to grain size differences. Today, a post-ECP anneal is standard in the process flow.
Scaling to 300 mm
Key to doing copper successfully in 300 mm is flawless scaling from 200 mm. Some see a solution in low-acid electrolyte chemistry — a high-resistance bath. Models predict it is less sensitive to wafer size. Preliminary data indicates models are fairly accurate.
Shipley sees some chemical impacts in the transition to 300 mm. "You're trying to control a non-uniform plating condition," said Thirsk. "When you apply a voltage to a wafer's edge, the potential gradient at its center is different than at the edges. You're trying to get the chemistry to operate across a range of different potentials and still provide a uniform film." Thirsk added that in scaling from 200 to 300 mm, slight straightforward changes in chemistry are required to provide process latitude.
The move to 300 mm is not expected to affect electrofill. Pete Bucher, senior product manager, LT ECD Products, at Semitool (Kalispell, Mont.), said his company has worked with 300 mm wafers and, from a uniformity and feature-fill aspect, detected no differences. "The issue is current density," explained Bucher, "which affects uniformity. We don't see any hurdles with 300 mm — seed layer and barrier. CMP is another story, because of its mechanical nature."
According to Novellus, the obstacles in the move to 300 mm will be comparable to those in the move to 200 mm. "There's still much development to be done," warned Beenen, "not only on electrofill, but in the integration of 300 mm into the process flow."
Integration and extendibility
Integration is seen as the next battleground by many involved in copper ECP — tool makers as well as end users. "This is why we subscribe to the module concept," said Applied's Cheung. "Everything required for integration is built into the tool." Based on this premise, Applied is working on what Cheung describes as "a foolproof solution:" a complete turnkey module system consisting of a seed layer, ECP and CMP tool, all integrated using the company's methodology.
Cheung believes ECP will persist over multiple generations and should not run into any serious problems down to the 0.10 µm node. "For 0.07 µm and beyond," he admitted, "additions will become necessary, such as electroless plating for the seed layer" (Table). Electroless is a chemically driven process in which the presence of a catalytic surface, such as a wafer with copper or other metal films, produces a spontaneous deposition of copper from the plating bath.
| Copper Metallization Roadmap | ||||
| 2000 | 2001 | 2002 | 2005 | |
| Design node AR | 0.15 7:1 | 0.15 7:1 | 0.13 8:1 | 0.10 8:1 |
| Metal barrier | Conformal Good barrier PVD barrier | COO 300 mm PVD/CVD | <50Å conformal | <50Å conformal |
| Cu seed | Morphology Overhang PVD Seed | COO 300 mm | COO CVD | Seed extendibility |
| Cu fill | Thermally stable Edge exclusion Void free Electroplating (w/bevel clean, anneal) | COO 300 mm | COO | Fill extendibility Electroless |
Ted Cacouris, Novellus' director of marketing, conceded that extendibility is a major question. "Will electrofill or electroplating last as long as needed — two to three generations? The pessimist's view is that the extendibility capability of a wet processing technology is limited," he said. "And much conjecturing is going on about doing something different, such as changing the deposition method again, to go to CVD." (See sidebar, "Process Monitoring for CVD Copper Seed Layer Deposition.")
Extendibility is a very unsettling prospect for end users. "Here they go through this whole integration and piloting activity, changing materials, processes and how they do business in the fab. Then you tell them this will only last one generation!" said Cacouris. Most agree this will not be the case, however, and that the investment will last two, possibly three, generations. "We've the knowledge and experience to extend the technology," said Cacouris. "We've demonstrated capability to work with 0.10 µm structures and aspect ratios as high as 10:1." Cacouris was quick to add that this capability is not yet at the manufacturable process level, but shows the technology is extendible to devices of those characteristics.
Chemistry perspectives
Electrolyte control is crucial in wet chemistry. Electrochemistry requires precise knowledge of the bath chemistry and its dopants. This influences the quality of the film plated to the wafer, as well as success with void-free features. Closed-loop control is an answer most tool manufacturers are implementing or considering.
The primary electroplating chemistry, the copper sulfate bath, has remained essentially unchanged for 30 years. It is being altered to allow for improvements in handling the desired aspect ratios, via fill and so forth. Beyond that, chemistry control is straightforward. State-of-the-art requires the daily replacement of 10% of the bath, whether used or not. Feed-and-bleed systems control electroless as well as electrolytic chemistries.
Traditionally, deposition tools have incorporated feed-forward and analysis-based dosing algorithms (using a cyclic voltametric stripping analyzer) to control bath organic additives. "But only a higher bleed-and-feed flow rate can actively control bath contaminant build-up, avoiding negative impacts on bottom-up fill mechanisms," said Olivier Blachier, manager of the Metallization Group of BOC Edwards (Santa Clara, Calif.).
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The increasing chemical consumption from the bath bleed and dump to drain, combined with the cost of treatment systems, have led to new approaches to chemistry management. BOC has developed a "remove-and-reconstitute" technique (Fig. 2), which recycles the bleed stream, doing a 100% organic stripping and replacement. The method replenishes the bath at a rate automatically varied by plating conditions and byproduct formation, and its centralized monitoring system simultaneously tracks five plating tools from different manufacturers.
Shipley's Thirsk believes there is a better understanding of the chemistry, particularly about how it affects plated film. "We've encountered previously unknown effects, such as overplating. When plating very narrow trenches, the chemistry that fills those trenches from the bottom up remains in the region during the plating reaction, and you end up with a bump over those dense trenches," he said. This is modified by varying the chemistry and regulating the plating current or going to a pulsed plating regime, where current is pulsed or its polarity reversed.
Shipley views 0.07 µm as an ECP challenge. "There are other influencing factors," said Thirsk. "The Roadmap calls for zero barrier layers at that point. If we worked with barrier layers common today, 0.07 µm trenches and vias would be smaller because they'd be constrained by today's layers. A pure 0.07 µm trench or via might be done with electroplating technology today; however, if we're using the same layer stack — a barrier layer plus a seed layer — and then expect electroplating to fill, it won't. Electroplating is extendible beyond 0.10 µm, but we must work on the layer stack's other elements."
Unexpected results seem the norm when ECP chemistries are tweaked. As Dr. Robert Small, EKC's R&D technical director, put it, "We've noticed that as engineers play with surfactants and other plating baths additives, they're getting secondary changes on the metal surface during polishing — sometimes pulling out actual sections of the copper crystals." This had not been observed a year ago. "By adjusting and depositing faster, we're pushing into new regimes. Shifts within annealing steps is another area where major changes are needed."
EKC believes that in two or three years industry needs will lie largely in the CMP area. "A requirement right now is for a material that anneals uniformly and consistently," said Small, stating that additives will play a role. "In a couple of years we'll be searching for a better plating bath," he predicted. "As CDs shrink, do we get a uniform copper crystal structure faster, or will it be more amorphous? That'll influence chemistries and topologies, because we see some effects with different planes, with copper responding to some of these chemistries during the polishing step."
As films get thinner, Small sees potential changes with extensions to current technology prior to CVD. "It'll probably be PVD for a while," he said. "It's unlikely we'll go electroless. Regarding barrier films, tantalum will still be around in three years, even though people are searching for easier ways for the peroxide system to polish into the barrier areas. Tantalum has a good track record; tantalum nitride is quite good and very resistant to copper migration to the film."
The porous dielectric
A major ECP hurdle is porous low-k material integration. In three years, low-k dielectrics will be in use, and most likely these will be porous materials. This poses problems for seed layer as well as ECP and CMP because these materials are soft and their mechanical strength weak. It will require the capability of doing ECP plating with perfect uniformity and planarity. Right now, everybody has some feature-size dependence.
"When you plate with the best method available — waveform plating — feature-size dependence is minimized, but is still there," said Applied's Cheung. "With porous materials, perfect planarization will be required. This is a problem since, because of additives, ECP plates smaller features faster and you end up with more plating on small features and less on larger ones. Balancing everything to get a perfect structure won't be simple."
Shipley is also concerned with porosity. "Current copper developments have probably postponed the adoption of porous films," said Thirsk, "but ultralow-k is on the horizon. We're working to understand it and have technology in-house for adding porosity to low-k films. The question is how to generate films that are porous but have closed cells."
Semitool's Bucher believes the solution to increasingly porous dielectrics lies before electroplating. "A porous material without a continuous liner over it would make it almost impossible to use today's PVD barrier and seed layers. The answer lies in the processes prior to electroplating, because if you put some sort of a continuous conductive layer on it, it'll be fairly straightforward to fill, irrespective of porosity."
Integration issues
According to Semitool's Bucher, the present ECP process works well enough. "The issues are integration-type issues," he said, "and these come into play after the CMP process."
Shipley views integration seriously. "One of our current efforts is to understand the integration challenges," said Thirsk. "We're working with Rodel to optimize copper deposition and CMP processes, and understand the effect that electroplating can have on CMP quality and vice versa."
Another concern lies in the materials area. "We never know what materials set is used," said Thirsk, adding that several low-k materials are being tried, and solutions are not always universal. "Just in materials integration there's a long road to travel. Materials and equipment suppliers are being asked to do more of this work up front, and provide it to the customer with enough data to make integration into the product easier. The challenge is to ensure that we've representative etch conditions or coating or CMP conditions transferable into the production environment."
Resolution of these concerns is not made easier by tweaks and changes. "There's a strong reliance between plating tool manufacturers and the electrolytes used in those tools," said Thirsk. "But there's a difference between engineering a chemical that must be produced and made to react consistently, and making an engineering change to the hardware. Tool manufacturers and end users must consider that the engineering that goes into the chemistry is not trivial. While a small equipment change is quickly implemented, it can require a very large chemical change, and the requalification process can take several months."
According to Novellus, offerings coming from different tool makers are comparable in capability and functionality. Novellus sees as one of the big changes the heavier emphasis by end users and suppliers in assisting with integration issues. "Here's where the battleground is right now," said Beenen.
"Most customers are relatively inexperienced with copper," said Cacouris. "Everybody's saying, By God, we better get into copper fast!' So they're moving aggressively, lacking the necessary fundamental understanding. When they try to integrate copper into their process they run into integration issues. Those who can help with those issues the fastest make the most progress."
The point to understand about integration is that semiconductor manufacturers are making large numbers of changes simultaneously. Copper is a new material for them, and electroplating a new process — dual-damascene itself is a new structure. Starting at the barrier seed level, most everyone is working with tantalum nitride, but this is a relatively new barrier. The copper seed must go on top, and this, again, is a brand new process. It is here where there is enormous competition on the PVD front to try to reach a leadership position in terms of the deposition of that barrier and seed. Then comes electroplating, and afterward probably one of the biggest challenges — copper CMP. "There's considerable interaction between the barrier, seed, the electroplating and the CMP process," said Novellus' Beenen. "At present, one of the least understood areas is the interaction of those three process modules."
Like its competitors, Novellus is convinced these integration issues will be resolved and does not foresee any fundamental technological barriers preventing this. "The challenges tool makers face are not limited to the features they'll be asked to electrofill; smaller feature sizes are a given," said Beenen. "End users are looking at increased aspect ratios, and, from a technological perspective, this won't just rest on the electrofill process, but between electrofill and PVD."
Extendibility — how far?
Like most, Semitool believes current copper fill process technology can probably be extended at least one technology node. "However, there are still manufacturability issues," Bucher said. "The integration process must be understood, and semiconductor manufacturers must also know when they see changes in seed layers, for instance, how that affects plating process results. In turn, they must understand how changes at the plating process' end can affect CMP."
CVD: an alternative view
 3. PVD techniques are expected to falter at the 0.10 µm node due to poor sidewall coverage, making it necessary to go to CVD copper for the conformal seed layers required for metallization at those dimensions. The SEM shows work done with CVD seed, confirming the applicability of the technique. (Source: Schumacher) |
Current CVD integration issues stem from the formation of impurities at the copper/barrier interface. Many freshly deposited barrier metals, especially tantalum, are highly reactive surfaces. These surfaces can degrade organic compounds resulting in interfacial contamination that increases contact resistance, preventing good adhesion. Optimizing barrier metal choice, CVD deposition process and precursor chemistry will resolve this.
"CVD copper provides the conformal seed layers for successful electroplating at 0.10 µm," said Cleary. "At smaller geometries, CVD copper can successfully fill aggressive contact via structures. And once the via plugs are filled during the CVD process, will the industry move back to PVD for bulk copper deposition? Time will tell."
It would appear that the most interesting challenge coming along for copper electroplating is the issue of combining the barrier and the seed layer and being able to deposit whatever that layer is at very small geometries. Potential solutions are being scratched out on the backs of envelopes now, but no one doubts it is will be one heck of a challenge. Although a working solution will be needed in some five years, for it to work it has to be arrived at during the next three. Lest we forget, the Roadmap continues to telescope. •
| Process Monitoring for CVD Copper Seed Layer
Deposition K.C. Lin, Materials Delivery & Analysis Products, MKS Instruments, Santa Clara, Calif. | |||
Before
copper can be electroplated, a thin, continuous, conducting copper layer
must be deposited on all surfaces of the patterned wafer. This includes
the sidewalls and bottoms of vias and trenches, which can have aspect
ratios up to 10:1 and dimensions close to 100 nm. CVD on the order of 15
nm is a method to get uniform films on such topography. The process, using
a complex fluorocarbon precursor (CupraSelect), is notoriously difficult
to control. However, process optimization and process control can be
greatly aided by process monitoring using an in situ quadrupole mass
spectrometer. Researchers at Applied Materials and MKS found that by
monitoring selected mass peaks during the multi-wafer process cycle (the
process "signature"), the wafer-to-wafer process repeatability can be
assessed and problems diagnosed1.
Figures 1 and 2 illustrate process signatures (mass spectrum trend charts) before and after process optimization. Mass peaks were tracked for the helium carrier, the copper precursor and a byproduct (labeled CupraSelect and tmvs). Figure 1 is the process signature for a 10-wafer process sequence recorded before optimization. The process cycle for each wafer consists of a helium purge, the deposition cycle, two helium purge cycles and a final pump cycle. The first few wafers show greater variation than do subsequent wafers. Previous observations had been that the film deposition on the first few wafers after a chamber idle period was slightly thicker and had poor adhesion. Also, there were precursor signal increases during the initial helium purge step before the precursor flow was initiated. During precursor injection into the vaporizer, the helium flow dropped sharply. These initial process signatures indicated the precursor vaporizer had a problem and the process recipe was not optimized.
Figure 2 is the process signature for a 7-wafer process sequence after optimization of the precursor injection system and the process recipe. The signal variation of the first few wafers is greatly minimized. The precursor and precursor byproduct residuals were reduced during the initial helium purge cycle. In general, the process signature is more reproducible. This new window on the process enabled process engineers to identify the causes of poor control and remedy them, leading to greatly improved process repeatability. • REFERENCES
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