Five-Level MEMS Create True Systems
Ruth DeJule, Associate Editor -- Semiconductor International, 4/1/2000
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Typically, MEMS devices are limited to two and three levels due to poor surface planarity. Two-level MEMS structures provide one layer of structural material and one to define the ground plane. Three levels allow the creation of gears with hubs, while a fourth can be used to define linkage arms that move above the plane of the gears, enabling a continuous 360deg rotation. The newly developed five-level technology consists of four mechanically active layers and an initial electrical interconnect layer, permitting complex interacting mechanisms, fabricated on moving platforms.
The basic process module of five-level MEMS consists of two primary films, sacrificial silicon dioxide layers and structural polycrystalline silicon layers, each ~2.25 µm thick. The process is consistent with standard IC fabrication -- low-pressure chemical vapor deposition (LPCVD), photolithography and reactive ion etch processes -- but modified for thicker films, optimized for mechanical integrity. In the five-level process, the sequence is repeated at least five times. With each deposition/etch cycle, protrusions are created, ~2 µm high mechanical parasitics that extend from the upper mechanical layer to the lower regions. In five levels, the protrusions could form 10-15 µm peaks, interfering with mechanical movement and straining the design. While MEMS devices can tolerate surface flatness an order of magnitude less planar than typical semiconductor devices, parasitics can easily collide with 9 µm high teeth and prevent gear rotation. Borrowing from advanced IC device manufacturing, chemical mechanical polishing (CMP) was modified and patented by researchers at Sandia to planarize each structural level. Once planarized, several photolithographic and film etch issues are alleviated, and designs are freed from constraints imposed by underlying topography.
The use of thin films, 2-4 µm, often has been cited as a major limitation to MEMS. Increasing film thickness produces greater out-of-plane mechanical stiffness, which is a cubic function of device thickness. In the five-level process, total stack height of five planarized levels is 12.5 µm, roughly six times thicker than a single layer, resulting in greater than 100X increase in out-of-plane stiffness. Ultimately, out-of-plane stiffness means better fabrication yield, improving both mechanical release and in-use stiction, the tendency of structures to adhere to themselves or their supporting surface.
 A ratcheting system fabricated with the five-level process displays a gear 100 µm in diameter. (Source: Sandia) |
Polysilicon films are deposited on both sides of the wafer, introducing stress and potentially causing bowing of the wafer, according to Paul McWhorter, deputy director of microsystems at Sandia. The fifth layer, however, displays a low-degree film stress gradient, alleviating film curl in released structures. Residual in-plane stress is less than 10 megaPascal. Using an interferometric technique, at least one polysilicon film exhibited a film curl m150 nm out-of-plane deflection at the tip of a singly clamped cantilever beam, 1000 µm long. The result implies structures with extremely large in-plane dimensions, such as 100 µm diameter gears, continue to be viable in the fifth-level polysilicon (Figure).
Beyond seven structural levels, process and design complexity, mask levels and film mechanical stress become prohibitive, said McWhorter. But current five-level MEMS and the potential for six have paved the way for even greater functionality of these remarkable tiny systems. •
