Step-By-Step Yield Analysis Based on Production Levels
Laura Peters, Senior Editor -- Semiconductor International, 2/1/2000
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Laura
Peters,
Senior
Editor
Using the techniques presented in this series to date, this current installment shows how the approach to yield analysis should differ between high-volume and low-volume production products, and for new products introduced on new versus mature technologies. The following describes not only the tools best suited for individual situations but the necessary data set required for each step in the analysis.
Using the step-by-step procedures shown in the table, the sequence of events for analyzing yield problems differs substantially for new products for which only a few lots have been run compared to products in full production. Nick Atchison and Ron Ross of TI's Silicon Systems recommend a complete test program for wafer probe be available as soon as the first wafers complete manufacturing. All parametric and functional test data as well as electrical parametric data must be logged and stored for each die by x-y coordinates. They further recommend using a total yield analysis package such as HyperYield, marketed by Heuristic Physics Laboratories (San Jose, Calif.). Detailed descriptions of how the tools used in this series work have been presented in previous installments and also appeared in articles published in TI's Technical Journal, Vol. 15, No. 4, Oct.-Dec. 1998.
For products running on a relatively mature technology with consistent yield and high volumes(>1000 wafers/mo), the steps shown will allow quantification of >99% of all yield losses. The first four steps quantify systematic and random defect yield losses, YS and YD, while the remaining steps are used to determine root causes of yield loss. When computing parametric yield limits, care must be taken to not count the same yield sensitivity more than once because of parametric correlations. Note that not every step needs to be performed in all cases. For instance, if YD is very high and YS is low, only steps related to systematic problems (steps 3-7, 8, 10) need to be performed. For each step in the procedure, the user should perform statistical tests of significance.
For new products, yield test structures should be included as part of each reticle field on the first two or three products for a new technology, enabling a more exact correlation of test structure results to probe results. •
| Steps for Yield Analysis | |||
| High-volume product(>2000 wafers) | Low-volume product(>500 wafers) | New product, new technology | New product, existing technology |
| Perform cluster analysis on 500 wafers to quantify YS and YD | Same | Run > 10 wafer lots containing large area yield structures, quantify YS' and YD' placing yield problems in order of magnitude | Critical area analysis (CAA) |
| Perform limited yield partitioning using KLA23XX data including probe bin overlay, calculate yield limits for each defect type with probability >5%, perform defect source analysis (DSA) | Same if KLA data is available, otherwise assume defect densities same as technology in general, adjusting killer probabilities and yield limits for lower volume using ratios of critical areas | CAA when product layout is complete | Use CAA and inline defect data to calulate defect yield limits |
| Perform parametric limit yield partitioning(>2000 wafers) | Skip | Calculate yield limits using test results from yield structures and CAA | Skip |
| Analyze test limited yield including test hardware and "twinkling" die | Skip | Perform twinkling die analysis after probing 10 lots, test hardware analysis after 20, (less data, perform DOE using same wafers on hardware setups or testers) | Skip |
| Construct wafer probe test Pareto(>20% population) | Skip | * | * |
| Construct histograms for tests in above Paretos(>0.2% loss) | Skip | * | * |
| Perform product sensitivity analysis (PSA) on parametric test performed at probe(>0.2% loss), perform virtual DOE if multiple sensitivites affect same probe test, actual DOE to verify subtle sensitivites | Same except compute the parametric (design and process) yield limits from PSA | Perform DOE on each new product, varying up to three critical parameters (per designer), extrapolate parametric spec limits, probe each wafer in lot, perform PSA to determine design sensitivity to electric parameters not covered by DOE lot | After 3 lots probed, compute parametric (design and proess) yield limits from PSA, perform DOE lot processing and analysis |
| Perform V0D0analysis by zone to tie yield loss to fab equipment | Can be performed but can only differentiate more pronounced effects on yield | * | * |
| Perform cluster analysis on wafers processed in different equipment units when yield losses vary significantly | Usually not enough data | * | * |
| Compare parametric (electrical) test data to in-line measurements | Usually not enough data | * | * |
