Metal/High-k Transistors Formed by Damascene Process
Peter Singer, Editor-in-Chief -- Semiconductor International, 2/1/2000
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Peter Singer,
Editor-in-Chief
Thinning gate dielectrics to below 2 nm is a critical part of developing high-performance transistors. According to Toshiba researchers, this means going away from the heavily doped polysilicon gates and SiO2 gate oxides used now to metal gates and high-k gate dielectrics. In work presented at SEMICON Japan, the researchers describe a damascene gate they say eases implementation of metal/ high-k gate transistors.
The advantage of metal gates over polysilicon ones is that metal gates do not suffer from gate depletion effects. The advantage of high-k dielectrics is that the higher the dielectric constant (k value) of the dielectric material, the lower the tunneling current density. Also, because of their greater capacitance, they can be deposited in a thicker layer than a silicon dioxide film with comparable electrical characteristics. High-k materials include Ta oxide, Ti oxide, Zr oxide and Hf oxide.
One factor driving the implementation of a damascene gate process is that it's difficult to use reactive ion etching to pattern thin gate oxides due to problems with plasma and thermal damage. Also, it's important to keep processing temperatures low to avoid increases in gate leakage current.
The damascene gate process developed by Toshiba requires a dummy gate mask. As shown in the Figure, after the source and drain are ion-implanted using the dummy gate mask, the dummy gate is removed without damaging the underlying layer. A fresh gate dielectric film is formed in a gate groove, and metal gate is patterned by damascene. In this way, the gate electrode is self-aligned with the gate groove, eliminating the need for additional gate lithography (compared with the replacement gate process).
In the damascene gate process, the processing temperature after gate formation can be lowered to 450deg C.
| Toshiba has developed a damascene gate process that enables the use of metal gates and high-k gate dielectrics. (Source: Toshiba) |
New Gas Combo Improves Dielectric Etch
A new combination of gases CF3I and C3F4 has proven more effective in generating the key radicals and ions used in dielectric etch applications. This should help overcome problems associated with low selectivity, microloading and etch stop, according to NEC Corp.
Today, dielectric etching typically is achieved with a mix of fluorocarbon gases. The plasma dissociates the gases into radical species and ions that act both to form a protective polymer layer on the sides of features and to perform the etching action at the bottom of the feature. In particular, CF2 radicals have been used as the main gas precursor for polymer deposition, and CF3 ions have been the dominant etchant for SiO2 films.
The problem with the existing approaches, according to NEC researchers Seiji Samukawa, Tomonori Mukai and Ko Noguchi, is that plasmas made from gases with a low molecular weight (CF4, CHF3 and C2F6) result in a small amount of CF2 and CF3 radical generation, as well as a large number of F atoms. This leads to less polymerization and reduced selectivity.
Gases with a higher molecular weight, on the other hand, result in more polymerization with a larger number of CF2 radicals, but fewer CF3 ions. It is also difficult to control the balance between the CF2 radicals and CF3 ions, according to NEC.
The solution is to generate selected radicals in fluorocarbon plasmas. In the NEC work, reported in Materials Science in Semiconductor Processing, Vol. 2, No. 3, CF3I and C2F4 gases were used to efficiently generate CF2 and CF3 radicals. The amount of these radicals was controlled easily by changing the ratio of the gas mixture. In addition to suppressing charge-up damage during contact hole formation, the gases also are environmentally attractive as alternatives to perfluorocarbons.
