100 nm: The Undiscovered Country
Alexander E. Braun, Senior Editor -- Semiconductor International, 2/1/2000
 | At a Glance | | |
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"The effect of stepper resolution enhancement techniques on image placement is a challenge lurking in overlay space," warned Alain Bojarski, vice president and general manager of verification systems at Schlumberger ATE (San Jose, Calif.). According to Bojarski, image placement often becomes a function of feature geometry. "This demands a rethinking of overlay measurement target designs, which haven't changed in years," he said. Another significant overlay hurdle resides in low-contrast targets resulting from extensive CMP use. "Maximizing metrology system image contrast will be a requirement where it wasn't an issue before," he said.
Gerald Yin, vice president of Applied Materials' Etch Product Group (Santa Clara, Calif.), indicated major manufacturers are moving toward 130 nm. "Some device structures already are at 110 nm," he said, adding that he believes the number-one issue for such fine geometry is CD control (Fig. 2). "Manufacturers want almost negligible CD variations because they're dealing with 0.005 µm or less CD variation across the wafer," he said.
As the industry approaches 100 nm, Tom Long, vice president of process module control solutions for KLA-Tencor (San Jose, Calif.), sees changes in transistor and isolation technology. "This begins with wafers, since 300 mm will probably be the size of choice at 100 nm," he said. Flatness requirements for wafers, particularly for 100 nm lithography, are complex. "You need a flatness of less than 100 nm across the entire site (2.5 x 4 cm) to print the necessary resolution," he said. "The move toward SOI wafers will definitely occur at that time, combined with shallow-trench isolation. Then, specifically in the transistor technology isolation area, the gate dielectric will move to higher-k materials, new materials."
Barriers and seed layers
Robin Cheung, general manager of the Copper Division at Applied, believes PVD is the approach for today's barrier technology. "Tantalum or tantalum nitride are used," he said, "because tantalum-based films provide the best barrier against copper diffusion into the dielectric. No contamination spreads to the rest of the silicon device."
Currently, PVD copper is used for seed layer production. Beyond 100 nm, Applied believes a CVD layer may be required, probably using PVD followed by CVD. Another approach would use PVD, adding electroless seed repair, making it possible to deposit Q50 Å of PVD, augmenting it with another 50-100 Å of electroless plating. This is to achieve better conformality and step coverage on the sidewalls for the seed layer to facilitate plating. Between 50 and 100 Å of continuous copper seed is needed on the sidewalls for plating. This means a minimum of 1500 Å copper seed deposited on the field. That creates an issue when feature sizes shrink from 200, 150 or 100 nm because of material overhang at the top opening of features. If deposited too thickly, vias are closed before ECP fill is attempted. "Source optimization is required to reduce the overhang and enhance step coverage for PVD," indicated Cheung.
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After polish comes passivation. Copper oxide is the worst material to work with, requiring passivation to remove it and stabilize the copper surface. Currently organic passivation is used; but it makes for a poor adhesion layer, and if a heat treatment takes place afterward, delamination occurs.
Low-k and 100 nm
Mark Beals, senior director of Dielectric Systems and Modules Product Group marketing at Applied, views the 100 nm challenge as delivering a <3.0 dielectric constant. "Low 3.5 FSG films will extend to the 130 nm device generation due to a lack of qualified dielectric of lower-k," he said. "However, this is where carbon-doped oxides with a dielectric constant of <3.0 will begin to be used on high-performance parts. Once qualified, it's easy to see that these new low-k CVD oxides will become the dielectric of choice for 100 nm devices."
Film stability is a low-k material concern. "We're looking at chemistry and lower deposition temperatures," said Beals, "to attain the dielectric constant and provide compatibility with copper and other temperature-sensitive materials that'll be used." Most low-k films are softer than undoped oxides and have increased adhesion problems. This is exacerbated by increasingly complex structures, combined with the use of CMP throughout the interconnect structure. With copper damascene technology, the addition of barrier and interlevel etch stops can mean up to five-layer film stacks at each wiring level. With up to 30 layers in a six-level structure, film stress and delamination become major issues.
Integration is another question. As a result of additional layers and barriers, the dielectric must be better isolated from the metallurgy. Metal films themselves have barriers, but the dielectric side also must deal with these -- sidewall barriers as well as layer-to-layer or coplanar barriers. This will be key in the 130 nm to 100 nm transition.
With copper damascene, blanket films provide more choices, Beals believes. "We may see the adoption of copper damascene almost exclusively," he said, adding that because improvements in the interconnect's performance are speed and reduced power loss, the solution requires cost-effective, simplified methods that can lower dielectric constant and resistivity of the wiring with less demanding aspect ratios for etched features. "CVD solutions have greater potential to provide mechanically stable, low-k materials needed in a simplified process flow," he said.
Inspection and metrology
"We're working on e-beam and shorter wavelength optical systems and methods for defectivity detection," said KLA's Long. "E-beam and optical combinations are necessary. E-beam is also useful for identifying subsurface electrical signatures," he said, adding that with damascene inlaid gate processing, all critical structures will be subsurface. "Presently, subsurface defectivity is best detected electrically."
CD-SEMs still have a bright future. Other technologies have been proposed, but with CD-SEMs there is still room for improvement. "A better understanding is needed of how CD-SEM image variations result from process variations," said Schlumberger's Bojarski.
"Beyond 100 nm, tool sensitivity/ throughput curves must be pushed upward," said Ofer Milstein, marketing manager of Applied's Process, Diagnostics and Control Business Group. "E-beam inspection will grow, but will still have throughput or previous layer defect limitations, so a combined solution will be needed. E-beam inspection will address resolution and high-aspect-ratio inspection issues, and work with other electrical defects such as copper voids."
E-beam probably will meet these requirements, but high-sensitivity and high-throughput tools are necessary to obtain data about complex structures and technologies. These tools will need UV capability to provide defect resolution and will have to provide quality information -- not just defect detection -- about the defect's composition, size and shape, identifying its source.
At 100 nm and below, metrology must provide information not only at the tool level, but the module level as well. "Then, we can work on closed loop or feed forward issues," said Milstein, "because we'll understand interrelations between different defects and how they result in capabilities or device parameters."
CD and overlay requirements are driving development of new metrology tools, requiring precise mechanical and optical tolerances. "With 100 nm lithography, we're looking at 3s CD control if 7 nm, and 3s procession for 1.4 nm; that's a quantum leap beyond what most metrology systems are capable of today," said Long. He added that overlay budgets are becoming tighter, with requirements of 3s values of 35 nm for overlay and 3s values of 4 nm for precision being projected.
Raj Chibber, director of engineering and R&D at Nanometrics (Sunnyvale, Calif.), views defect detection as a challenge. "The problem is how to do defect detection down to the 10 and 20 nm level," he said. "Currently, we're having a hard time doing optical defect detection at that level, even on unpatterned wafers. Optically, height measurement can be done accurately to 1 nm, but lateral dimension measurement at 100 nm is difficult."
Gary Ray, director of integration for Novellus Systems (San Jose, Calif.), expects that, disregarding dimension, matters like control of uniformity, deposition rate, particles and contamination will be pushed harder. "With increasingly longer interconnects acting as antennas to attract charges, an important area is plasma damage on thin gate materials. Gap fill and associated step coverage for barriers and seed layers will be pushed harder as feature aspect ratios increase," predicted Ray, adding that it will be hard to improve dielectric constant in interlevel insulators.
Gate structures are moving to an inlaid model, a la damascene, when viewed against traditional polygate structures. "Defect mechanisms for damascene-type structures are different from those of subtractive structures," said KLA's Long. The defects for subtractive structures are generally static and on the surface, while for damascene structures they are dynamic -- can grow during subsequent process steps -- and subsurface. "Damascene structures are becoming dominant, as we see in shallow trench isolation, inlaid gate and copper interconnect," said Long.
In the BEOL, KLA believes copper will dominate from 130 nm on, combined with low-k dielectrics. "Existing electroplating processes may not work at sub-100 nm geometries," stated Long, adding that development of electroless copper plating and new copper physical deposition processes may be necessary. "These could change defect mechanisms as we know them today," he said.
Jean-François Daviet, director of the RTP Group at Mattson Technology (Fremont, Calif.), anticipates the formation of ultra-shallow junctions on fragile 300 mm wafers will be difficult. "High ramp rates and short thermal cycles are required to obtain sub-400 Å junction depth with boron doping," he pointed out. "Boron atoms diffuse quickly in most materials, and boron in silicon is subject to various TEDs caused by crystal imperfections -- doping, defects, oxygen, etc. This enhances diffusion, even at relatively low temperatures, starting at ~700degC. Spike anneal with a lamp RTP or laser annealing can achieve required process results but is costly and complex."
Copper integration will be difficult. "The unexpected and damaging side effect of the copper self-annealing phenomenon was an unpleasant surprise," Daviet said. After ECD, copper re-crystallizes uncontrollably at room temperature, creating major process control problems. This affects subsequent steps, especially CMP. "Each copper layer must be annealed prior to each CMP. Currently, this is performed at approximately 400degC in a very tight, oxygen-free environment," he said, "preferably right after the ECD step." This is a costly obstacle to copper interconnect implementation because each of the six -- soon eight -- copper layers requires an annealing step.
Additionally, copper is a notorious poisoner of silicon devices, diffusing quickly into almost any material. "Even at the low temperature needed for anneal, copper diffuses quickly even in the best barrier layers," said Daviet.
Lithography hurdles
Lithography has always kept apace of IC developments, providing solutions for shrinking geometries and improved performance. The industry has a vested interest in extending optical lithography as far as it can go because its reliability has been outstanding.
"Right now, there's 180 nm production going on 248 nm tools, and development work underway to shrink this to 150 nm," said Bill Arnold, chief scientist at ASML (Veldhoven, Netherlands). "During 2000, IC makers will consider 130 nm using DUV tools." Arnold added that 193 nm lithography is progressing, although it has not yet reached production levels (Figs. 3, 4).
There are ways to extend optical lithography well below 100 nm. Companies like ASML are working to improve the manufacturability of low-k factor lithography. That means improvements in off-axis illumination, OPC and phase-shifting. "Best guess is that 193 will take us to 100 nm and perhaps a little beyond," said Arnold, "and 157 nm could take us to 70 nm."
David Hemker, managing director of new product development for Lam Research (Fremont, Calif.), views major challenges to breaking the 100 nm barrier in lithography, materials and device structures. "In lithography, to define sub-100 nm dimensions using DUV and EUV exposure requires chemically amplified (CA) resists that are less robust than traditional ones," Hemker said. "They must be applied thinner, are more sensitive to plasma etch environments and erode faster during etching."
Many use hard mask materials to sidestep this problem. For example, to etch a polysilicon gate stack, a thin (~200 nm) layer of silicon dioxide or silicon nitride is layered over the polysilicon. The CA resist is applied and the hard mask etched; the mask mitigates problems caused by thin, rapidly eroding resist. It also enables the poly to be etched with a selectivity of 20:1 - 50:1 to the hard mask, which is greater than what can be achieved with a photoresist mask.
Hemker believes etch processes with good selectivity for the new high-k gate dielectrics will have to be developed for metal gates. "Additionally, in the copper dual-damascene flows, low-k dielectric selection will have to take into consideration the feasibility of plasma etching <100 nm dimensions and overall integration into the process flow," he said.
For Harry Sewell, director of technology for SVG (San Jose, Calif.), the transition of lithography from 248 nm DUV wavelengths to 193 nm, and the implementation of increased NAs on optical lithography tools are impediments to crossing the 100 nm node. "Lithographic tools at 193 nm are being used in development, and semiconductor processes are being worked out. Lithography at 193 nm will be in production for 100 nm."
Sewell believes reticle CD control is of major importance at 100 nm. Since the overall CD variation budget is small, contributions from all tools become critical. These include thickness variations during resist processing, CD control throughout the exposure process and CD control during developing. "Close fine-tuning between the track and scanner is a must to minimize overall CD budgets," stated Sewell.
In two years' time, SVG expects 193 nm lithography to be in line with 0.75 NA lithographic tools for routine production of 130 nm node lithography, with lithography at the 100 nm node in final development.
David Markle, vice-president and CTO of Ultratech Stepper (San Jose, Calif.), believes 157 nm lithography will develop quickly. "There are problems," he admitted, "but we've made fantastic progress" (Table). One of these problems lies in materials. "It'll be difficult to find calcium fluoride of sufficient quality and quantity for blank sizes greater than 150 mm in diameter," he said, adding that at that wavelength it is the only optical material that can be used.
Another issue is resist. As Markle puts it, "Resists used at 248 and 193 nm are unsuitable for 157 nm. The resins are so absorbent at 157 nm that they can't be used, and the fact 157 nm tears apart organic molecules does not simplify the choice."
Doug Anberg, Ultratech's director of product marketing, weighs in with another issue: "For 157 nm, you must pass the light through an inert environment or a vacuum. Oxygen concentration must be reduced to ppm levels along the optical path because it's a very strong absorber." Many AR coatings are composed of oxides, making them unacceptable because of oxygen content. "New materials are needed for AR coatings," he concluded. In its R&D tool, Ultratech addresses environmental control by purging with nitrogen. On full-scale production tools, however, getting a wafer in and out of a controlled environment with reasonable throughput presents major engineering challenges.
Ultratech is optimistic about 157's extendibility. "We can increase NA, go to different illumination techniques separately or in conjunction with phase-shift masks as well," said Anberg. "We can extend it just as i-line and DUV were extended. However, once you've a high-NA machine and have exhausted extendibility with phase shift, then it'll be EUV or SCALPEL."
EUV systems will be complex. "We're talking about all elements, including the reticle, being reflective," said Anberg. "This makes reticle blanks expensive and the system transmission an issue; the radiation source is complex, and everything must be in a vacuum, including wafers. Both EUV and SCALPEL have throughput limitations."
Bets seem to be on EUV over SCALPEL, because it is an all-reflective technology and few materials are needed -- just mirrors. However, due to the wavelength, these must be polished with exquisite accuracy. "You're dealing with a wavelength 27x shorter than i-line," pointed out Anberg.
A result, however, is high resolution with a moderate NA. A 0.3 NA all-reflective system could probably go to 30 nm, making EUV more than just a one-generation solution. Estimated throughput from such a system looks good: up to 80 300 mm wph -- a crucial difference between EUV and SCALPEL.
Beyond optics
Eventually, fundamental physical barriers will be hit. A K1 factor of less than 0.25 is impossible, as is an NA of 1. Due to absorption, there is not much prospect for a wavelength shorter than 157 nm used in a purely refractive optical fashion, with a glass lens or reticle; likewise, NAs greater than 0.9 are probably impractical for the field sizes required.
The industry is trying to determine what happens after optical lithography (Table), and options are being narrowed. Proximity X-rays and some of the direct-write e-beam options have been discarded, mostly leaving EUV and SCALPEL.
| Contending Lithography Systems | ||||
| Lithography | 157 nm | EUV | SCAPEL | Ion Beam Projection |
| Principle | Projection optical lithography with 157 nm F2 laser | 4x all mirror scanning projection, each substrate coating by multilayer (~80 layers Mo/Si) wavelength 11 or 13 nm generated by laser producing plasma | 4x E-beam projection; tungsten scattering mask. | 4x ion beam (h+, He+) projetion, binary substrateless mask. |
| Prospects | 70 nm, > 100 200-mm wph, depending on resist | 100 to <30 nm nodes, 50-80 300 mm wph | 100 to 50 nm node, lowest NGL reticle ost, throughput 20-30 300 mm wph at 100 nm | 100 nm to less than or equal to 50 nm nodes, >35 300 mm wph at 100 nm, 20 300 mm wph at 50 nm |
| Issues | Reticles, pellicles, resis, lens cost, environment | Defect-free reflection masks; contamination control; optics including ML coatings; source: power, lifetime (debris) Co0; vacuum stages | Spae harge limits, wafer heating | Stenil mask osts, unknown image plaement yield, writing time, space charge |
SCALPEL is a true departure because it is electron-based lithography. To mitigate risks, ASML has decided to go into it through a joint venture with Applied Materials. "SCALPEL is attractive for those whose business depends on a lot of mask usage," said Arnold. SEMATECH has consistently projected costs of SCALPEL masks to be the lowest of all the various NGL alternatives.
Undeniably, 100 nm will require considerable R&D, engineering and capital equipment investment. However, the actual "breaking" of the
100 nm "barrier" appears to be another arbitrary milestone on an infinitely long road, just like Mach 1 or the much-hyped crossover into the "new millennium." •
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