High-Density Packaging: The Next Interconnect Challenge

		At a Glance
	For high-performance ICs, the package is starting to play a larger role in determining performance and cost. Packages are becoming more efficient in protecting the IC, handling the thermal load and routing more signal connections through smaller spaces. They also are starting to handle power distribution for the chip and house passive devices that ordinarily would take large amounts of board space. Multichip packages and 3-D methods provide effective ways of packing ICs into smaller spaces as well as alternatives to system-on-a-chip integration.

Semiconductor technology has progressed to the point where packaging plays an integral role in the performance of a semiconductor device, in addition to protecting the die and passing connections through to the next level. The 1999 ITRS Roadmap addresses this fact,¹ stating in the beginning of its assembly and packaging section: "There is an increased awareness in the industry that assembly and packaging is becoming a differentiator in product development. Package design and fabrication are increasingly important to system applications. It is no longer just a means of protecting the integrated circuit (IC), but also a way for the systems designer to ensure form fit and function for today's products -- spanning consumer products to high-end workstations."

In recent years, the industry has recognized that on-chip interconnects are the limiting factor in high-performance ICs,² requiring much attention. Off-chip interconnects are becoming a part of that limitation. In fact, some are saying interconnect, not MOSFETs, soon will dominate performance and cost.³ Some believe interconnects that people are intending to put on the chip should be placed in the package instead (Fig. 1).

The definition of high-density packaging seems to vary. Some define it by the I/O pitch or the interconnect pitch. Others define it as any package that has to be co-designed with the chip to perform as needed. Regardless of the definition, it is understood that high-density packages are a requirement for high-performance ICs and systems.

Chip-substrate interface

The interface between the chip and package is becoming blurrier. More options exist now for connecting them. The main change is an increased use of flip-chip attachment in the package, but there is much more. Many bumping contractors also offer redistribution services. Though redistribution is done on the chip -- actually on the wafer -- it is considered a packaging operation. A fab may choose to have a contractor perform redistribution to keep from tying up lithography equipment used for smaller pitch on-chip interconnects.

Flip Chip Technologies (FCT, Phoenix), Unitive Electronics (Research Triangle Park, N.C.) and Pac Tech (Nauen, Germany) all offer redistribution with benzocyclobutene (BCB) as the dielectric. Many other companies offer merchant bumping and redistribution services, and the list continues to grow.⁴

1. In more cases, multiple chips are placed in one package, since they form a logical unit, but are easier to realize using more than one die. (Source: Abpac)

Polymer Flip Chip Corp. (Bellerica, Mass.) has been offering flip-chip technology using conductive polymer bumps. The company claims significant advantages over solder-based flip-chip technology, with fewer process steps, process temperatures below 160degC, and stencil printing capability for 75 µm bumps on a 125 µm pitch. The lower process temperature allows the use of less expensive substrates. Many consider the state of the art for production solder-based processes to be a 225 µm pitch, though some have demonstrated pitches down to 50 µm.

Gold ball bumping has been used in cases where state-of-the-art pitches are not required. Since a wire bonder is used to make the bumps, it is restricted to peripheral I/O applications and does not necessarily qualify as a high-density process. It does qualify as a low-cost process for companies transitioning to flip-chip technology.

Chip-scale packages

Chip-scale packages qualify as high-density packaging in the sense that packaging material is minimized while performing some packaging function. Also, many can be viewed as functionally equivalent to flip-chips with enhancements. There are 100 different CSPs, and each needs to be evaluated on its merits.

As the number of CSPs keeps increasing, it is important to remember they have strengths and weaknesses. Weaknesses are the cost of the reduced size, and they must be compensated elsewhere in the system. This could result in a net overall advantage. For example, if a CSP is strong with regard to mechanical compliance and thermal properties, but weak in hermiticity, a conformal coating at the board level could be enough to compensate. If the application requires reworkability, then the board would not have a conformal coating, and the packaged devices would need good hermiticity.

CSPs inherently provide a cost advantage, not only because of reduced material usage but also in process simplification. Wafer-level packaging, one of the main subdivisions of chip-scale packaging, has great promise for reducing cost because it takes advantage of "wafer economics" and contracts steps such as probe and final test. This cost advantage must be factored in when evaluating the overall system design that includes the CSP.

CSPs reduce the size of the systems in which they are placed. In that way, they are a part of high-density packaging from a system-level view.

Multichip packages

Multichip modules have seen use in high-reliability applications and some high-performance applications to keep components together that act as a single unit. In some cases, simple multichip packages are referred to as complex ICs because the component dice logically belong together but are not realized as a single die. Depending on the application, this could be an analog amplifier with a gallium arsenide rf mixer/driver, or a processor with external cache memory. Many leading-edge processors are realized as a module, containing a packaged CPU and commercially available devices for the cache. In higher-density applications, multiple unpackaged dice are placed in one module to save space.

The term multichip package is starting to emerge, underscoring the difference between the newer designs from the ingrained concept of a high-reliability multichip module. Multichip packages for consumer devices do not need the same hermiticity or resiliance to severe mechanical shock as a classic multichip module, and they can simply be laminate substrate packages in many applications.

The particular implementation of multichip packages varies according to application. For the rf amplifier/ mixer application, the two chips are made of silicon and gallium arsenide, respectively, so they have to be made separately. For the processor application, the cost effectiveness of available memory leads to the choice of external level two cache.

A recent paper by Evan Davidson⁵ of IBM suggests separating system functions into more than one die can be preferred, so multiple dice are used by choice rather than necessity. As the die gets larger, on-chip wiring becomes longer and slower. Using what Davidson calls "obese" on-chip wiring traces to compensate for the length increases the number of metal layers required. Wiring traces between dice can have lower resistance than long on-chip traces. If the chip is laid out to minimize long traces, then separated into smaller die, net performance can improve.

On the subject of long on-chip interconnects, Leonard Schaper, director of the High Density Electronics Center at the University of Arkansas (Fayetteville, Ark.), said: "When you look at the total delay, if you size your off-chip drivers correctly, you can actually get an off-chip path that takes less time than an on-chip path. You are actually better off, once you get above 5 or 6 millimeters of wire length, to go off the chip than to try to run those long wires on-chip with very thin metal. And if you make the metal thicker, you can't make the design rules you want."

The long lossy line problem is not the only difficulty in making larger devices. As the die becomes larger, a single killer defect can disrupt more functions in disabling a single die. A larger die also can result in a net loss of functionality created per wafer, due to the tiling problem at the edge of the wafer. According to Davidson, the maximum die size seems to be 15 x 15 mm. "From what I've seen, once you start getting above 15 millimeters on a side, the yield starts dropping off to the point where you question whether you want to manufacture such large chips, unless it's array with redundancy; then you can do it. But if you are putting a lot of logic function on a chip, and it's getting that large, there's a good chance the yield will make the chip unusable. You'll get very few good chips off of a wafer."

Alpine Microsystems has a silicon substrate interconnect system for multichip packages.⁶ Layers of copper for power, ground and signal traces are built on a silicon substrate. Individual dice are flip-chip attached to these substrates, and the substrates are connected to each other in a "microboard." Figure 2 shows one of these microboards used in a personal digital assistant application.

2. Processor, memory and memory controller chips are all connected on a silicon "microboard," which is attached to a circuit board in a portable computing application. (Source: Alpine Microsystems)

3-D methods

Stacking two, three or more memory dice in a single package has been an emerging trend over the last few years. Stacking a heterogeneous set of dice also is an emerging trend. Most methods involve peripheral interconnection, but some are providing area array interconnection.

Many companies, particularly in Asia, have been stacking dice physically without connecting them to each other. Sharp Microelectronics recently announced a three-die stacked memory device (Fig. 3). The die on the bottom is largest, the die on top smallest, and they are all wirebonded to the package. Many companies use this scheme to put two dice in a package. Since the dice are not connected to each other, this scheme simply saves board space.

3. Thinning and stacking dice within a package increases packaging efficiency and saves board space. (Source: Amkor and Sharp)

Dense-Pac Microsystems (Garden Grove, Calif.) offers many commercial and high-reliability memory devices in the form of interconnected stacks. The company's M-Densus technology uses metal traces on the side of the stack to form the interconnects. The stack acts as a single device with more memory, as opposed to independent memory dice that are colocated.

Irvine Sensors' ( Costa Mesa, Calif.) Neo Stack technology places multiple dice in a "neo wafer," or a wafer-shaped carrier. The neo wafers are stacked, and after singulation, interconnects are completed on the sides of the stack. Since this method uses singulated die, it can be a heterogeneous stack.

Recent work at the Korea Advanced Institute for Science and Technology (KAIST, Taejon, Korea) and LG Semicon is similar, though it requires that the dice to be stacked be made in a strip on the wafer.⁷ Solder balls are placed on the side of the stack for next-level interconnect.

3-D Plus Electronics (Buc Cedex, France) produces light-weight heterogeneous cubes. The dice are bonded to individual flex substrates that have copper metalization. These chip-on-flex pieces are placed in a jig and encapsulated. Sawing reveals the I/O connections. The cube is plated with Ni/Au, and patterned with a laser to make the interconnects.

A collaborative effort in Europe has developed a method in which dice are embedded in a 3-D interconnect structure.⁸ A copper interconnect structure, using BCB as the dielectric, is built on a substrate, and thinned dice are placed in the structure as the layers are built up. This is a case of one or more dice being placed on a redistribution structure, instead of redistribution being done on the die.

In some specialty applications, flip-chip on chip has been used. Two dice are attached face to face, and the larger of the two has peripheral bond pads for wirebonding. Electronic Visions (Phoenix) has been involved with work done at MIT⁹ and Rensselaer Polytechnic Institute on thermocompression bonding of wafers face to face. Thermocompression at 400degC for 30 minutes seems to make reliable copper-to-copper bonds.

4. This backside view of a thinned wafer shows through-silicon contacts, including alignment marks (a). A close-up view shows the insulating oxide "collar" for the bump-like contact (b). (Source: Tru-Si Technologies)

Tru-Si Technologies (Sunnyvale, Calif.) recently announced its stacked wafer-level packaging technology, based on its through silicon contact technology.¹⁰ Contacts are embedded in the wafer from the front side, and after wafer processing, the wafer is thinned to reveal the contacts through the back of the wafer (Fig. 4). The stacking starts with an interposer wafer with through contacts that eventually will be the external I/Os. A device wafer is bonded face to face with the interposer, and the device wafer is thinned to expose its through silicon contacts, which act as bumps. Another device wafer is bonded face down onto those "bumps." This thinning and bonding can continue as needed. This approach can allow a device to be realized not only in a smaller area, but also a smaller volume, depending on the amount of thinning that takes place.

Also, the company points out that this is a way to realize a "system-on-a-chip" type device without mixing technologies on a wafer. The system would be realized in a stack, and technologies like logic, analog, rf and memory can be made on separate wafers, each optimized individually. Integrating any two on the same wafer could involve process tradeoffs and yield challenges.

High density substrates

Microvia substrates are finding wider adoption in high-performance applications.¹¹ They are mostly organic build-ups, and many are flex. In addition to package substrates, some find use as high-density patches for circuit boards. (See Table for a list of companies providing microvia substrates.)

Microvia IC Package Substrate Suppliers
AMITEC (Israel)	K & S (MMS X-LAM) (U.S.)
ASTI (U.S.)	Kyocera (Japan)
Canon (Japan)	NEC (Japan)
Compeq (Taiwan)	NTK (Japan)
Fujitsu (Japan)	Sanmina (U.S.)
Hitachi Cable (Japan)	Samsung (Korea)
Hitachi Chemical (Japan)	Sheldahl (U.S.)
Ibiden (Japan)	Shinko (Japan)
Daisho Denshi (Japan)	STP (Germany)
IBM (Japan, U.S.)	SMI-Electronic Devices (Japan)
JCI (Japan)	Toppan (Japan)
JVC (Japan)	W.L. Gore (U.S.)

(Source: TechSearch International Inc.)

The methods used to create these substrates vary greatly. ASTI (now Honeywell, Costa Mesa, Calif.) uses a build-up of flex with 0.5 µm sputtered copper. X-LAM Technologies (Milpitas, Calif.) uses an all-thin-film process to build up layers on its substrates. W.L. Gore (Eau Claire, Wis.) uses copper film with its expanded PTFE material.

Interconnect traces parallel to the build-up layers can be made with relative ease, but filling the vias can be a challenge, especially now that state-of-the-art via diameters are in the neighborhood of 25-50 µm. Screen printable conductive polymer materials have been developed to fill these microvias.¹² Ceramics have been used for many high-performance ICs, modules and specialty devices like surface acoustic wave (SAW) filters. Ceramics have a closer CTE match to silicon and higher thermal conductivity than laminates, and are considered to have higher dimensional stability than most laminate materials. This stability allows finer patterning for wiring traces than on laminates, though laminates are less expensive.

The importance of dimensional stability is not just mechanical. For high-speed communication, the interconnect lines in the package are essentially transmission lines, and the impedence properties of those transmission lines can change significantly with an anisotropic thermal expansion. Many laminate materials have an anisotropic CTE.

Another advantage of ceramics is low loss at high frequencies. In general, properties such as dielectric constant are less sensitive to frequency for ceramics, though there are exceptions. Their dielectric constants may be higher than those for flex or laminate materials, leading to slower propagation speeds, but high-speed transmission has little value if the signal dies. Also, loss at much higher frequencies than the data rate must be considered. It is generally accepted that five or more harmonics are needed to make data waveforms with adequate rise and fall characteristics. If loss varies too much over that range, transmitted waveforms will be severely degraded.

Integrated passives

Most of the real estate on a board, and a significant portion of the real estate on a multichip package substrate, is taken up by passive components. They can be made smaller, but if they get too small they will be incredibly difficult to place on the board or in the package. They can be made on the chip itself, but silicon real estate can be too expensive for this. The answer is to embed passives in the package substrate. Integrated passive components are created using well-understood thin- and thick-film techniques.

5. In these RF applications, decoupling capacitors and RF passives are a part of the package, reducing board space. Passives are integrated in a multilayer LTCC package in (a), and in (b) discrete devices are bonded to a substrate containing thin film pass ives. (Sources: (a) DuPont and (b) Intarsia)

One prominent method is to embed them in ceramic cofired substrates. Cofired systems are preferred because all the components experience the same thermal history, providing consistent electrical properties at all levels within the stack. Low-temperature cofired ceramics (LTCCs), such as DuPont's Green Tape, are ceramic-filled glass systems that retain a high viscosity throughout the firing process. This means the LTCC does not flow and mix with the other materials used to make the passives (Fig. 5a).

Thin-film methods are gaining popularity for making integrated passives (Fig. 5b). Sputtered tantalum nitride (TaN) seems to be the most popular thin-film resistor material. Aluminum oxide, tantalum oxide, silicon nitride and BCB are all used as capacitor dielectrics. Spiral inductors made of copper also are used in some RF applications.

Integrated passives also are made in their own array. Putting all the passives for a board in one small package can be easier than placing many small passives. Companies specializing in these devices include AVX (Myrtle Beach, S.C.), Intarsia (Fremont, Calif.) and California Microdevices (Milpitas, Calif.).

Distributed filtering also can be done using the characteristics of the substrate material itself. In these cases, a higher dielectric constant material is desired for the substrate because the distributed filter ends up being smaller. This would be another reason to investigate ceramics.

Conclusion

Though there have been many packaging innovations in the last 10 to 15 years, there has been no need for major changes in methodology in packaging. Packages have done little more than protect the die and pass signals and power through. Chip-scale packages do most of that now. Larger packages are being called on to provide much more than a protective function. They help condition and distribute power, connect chips to each other, and house passives. They are a part of the interconnect continuum.¹³ Interconnects will determine the performance and cost of upcoming electronic systems; and advanced, high-density packages will play a vital role in connecting on-chip functions to each other, as well as to the outside world. •

3-D Plus www.3d-plus.com

AMITEC www.amitec.com

ASTI www.electronicmaterials.com

California Micro Devices www.calmicro.com

Canon www.canon.co.jp

Compeq www.compeq.com

Daisho Denshi www.daisho-denshi.co.jp

Dense Pac www.dense-pac.com

Dow www.cyclotene.com

DuPont www.dupont.com/mcm

Flip Chip Technologies www.flipchip.com

Fraunhofer IZM www.izm.fhg.de

Fujitsu www.fujitsumicro.com

HiDEC University of Arkansas www.hidec.uark.edu

Hitachi Cable www.hitachi-cable.co.jp

Hitachi Chemical www.hitachi-chem.co.jp

Ibiden www.ibiden.co.jp

IBM www.chips.ibm.com/products/interconnect/

IMEC www.imec.be

Intarsia www.intarsiacorp.com

Irvine Sensors www.irvine-sensors.com

KAIST www.kaist.ac.kr

Pac Tech www.pactech.de

Polymer Flip Chip Corp www.pfccorp.com

Tru-Si Technologies www.trusi.com

Unitive Electronics www.unitive.com

W. L. Gore and Associates www.gore.com

X-LAM Technologies www.x-lam.com

JCI

JVC www.jvc-victor.co.jp

Kyocera www.kyocera.com or www.kyocera.co.jp

NEC www.nec.co.jp or www.nec.com

NTK www.ntktech.com

Samsung www.samsungsemi.com

Sanmina www.sanmina.com

Sheldahl www.sheldahl.com

Shinko www.shinko.co.jp

STP www.stp.de

SMI Electronic Services www.sumikin.co.jp/docom/electdev/lsi.html

Toppan www.toppan.co.jp

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REFERENCES

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The High-Density Network

As more functionality is placed on the chip, more interconnect-related items are drawn closer to the chip. We are all familiar with network communications in a wide area network (WAN). Many of the principles behind wide area networking have been leveraged for use in local area networks (LANs). With the advent of RAMBUS, the network communication approach is being pulled into the PC box to help processors communicate with memory. In upcoming technology generations, network communication will be required between elements on the chip itself.a Interconnects in a package substrate, or even on the chip itself, will not merely be wires; they will be network connections. For example, some of IBM's advanced computing devices will have multiprocessors in a package, and communication between the processors must be handled in the substrate. At the same time, these interconnects are becoming smaller. More efficient use of material is one necessity; innovative thinking also will be required. Many methods are being used and developed to make more efficient use of material. Three-dimensional packaging is one set of innovations, but more are needed. Bringing the practical support needs of network connections along with the connections themselves will require quite a bit of innovation. One of the concepts behind Tessera's WAVE technology is to enable power and ground distribution in the package. Instead of using the package as a pass-through for running multiple power connections from the board to the chip, the package takes input power through fewer connections and distributes it to the chip. For chips that require a large number of power and ground connections, this is roughly analogous to putting an electrical substation near a large electrical load rather than routing hundreds of extension cords to it from the power plant. Of course, "multiple extension cords" can be the optimum solution for a given application. In some cases, though, the extension cord analogy describes an ad hoc solution, where most of the focus was on making the load (or IC) perform its function, rather than optimizing the overall system. Practical matters, like power distribution, are part of the solution. Another part of the solution is optimizing circuit design to take advantage of distributed functionality. This means decisions about creating a system on a chip, as opposed to a system in a package or a chip set, are based only on optimal grouping of functions, rather than seeing how much can fit on a die. As the 1999 Roadmap notes, "The (chip/package) interface is blurring, and it is becoming more important to consider the chip, package and printed wiring board together." The interconnects in a package are a part of the interconnect continuum, and those interconnects should be used more to tie functions together by choice, rather than by "necessity." The ultimate in recognizing the value of interconnects may occur if through-silicon contacts are used to make 3-D stacks. "Sacred" silicon, which normally would hold many transistors or other devices, would be sacrificed for passing connections through. Clearly, a detailed cost/benefit analysis would be needed. There would be many factors to consider, especially yield and performance. If the yield for a large-die system-on-a-chip is poor enough, more silicon would be wasted than for smaller, higher-yielding dice with through-silicon contacts. Also, the performance gain from processing different technologies on different wafers should be considered. Right now, chips are components of networks. It may not be long before chips contain networks. When that happens, all of the practical things networks need will have to be implemented on, and sometimes in, the silicon itself, instead of just around it. • a. B. Dally, "Interconnection-Oriented Computer Architecture," Technical Program of the 1999 International Interconnect Technology Conference (IITC), May 24, 1999, IEEE.