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Nitride Gate Dielectric, Poly/W Electrode Enable 100 nm CMOS

Peter Singer, Editor-in-Chief -- Semiconductor International, 1/1/2000

Continued scaling to 100 nm (0.10 µm) and beyond will require a variety of breakthroughs, including suppression of electron tunneling through extremely thin transistor gate dielectrics; reduction of electrical resistance in a very narrow gate electrode; the ability to reduce the pitch, or spacing, of gates while keeping their contact resistances low; and the ability to suppress unwanted short-channel effects adequately.

Last month, at the International Electron Device Meeting (IEDM), researchers from Hitachi described how they built ultra-small 0.1 µm CMOS transistors that overcame all these problems. A key element of their success was to use a SiO/SiN stacked gate dielectric with a polysilicon/tungsten gate electrode.

The researchers say the SiO/SiN gate reduces the tunneling current by about one order of magnitude compared to an SiO2 or SiON layer with the same electrical thickness. The polysilicon/tungsten gate electrode above the dielectric gate stack reduces the gate resistance. Also, since the gate structure does not need silicidation on the gate, it's possible to reduce the thickness of the silicide on the source/drain contact area. This helps prevent junction leakage current in the shallow source/drain junctions.

In the IEDM paper, the Hitachi researchers describe how a thicker layer of silicon nitride can be used to achieve the same gate capacitance, since silicon nitride's permittivity is twice as high as silicon dioxide's. "In order to increase gate capacitance to boost the driving current, nitride is one of the most promising materials which reduces direct tunneling current through the gate dielectrics," they note. The gate stack was formed by steam oxidation followed by LPCVD of Si3N4 and N2O hardening.

Shallow source/drain extensions were fabricated by low-energy ion implantation (below 5 keV) of As and BF2 for the NMOS and PMOS transistors, respectively. They were combined with the carefully optimized punch-through stoppers by BF2 and P implantation. •

Nitres Team Achieves Highest Power Output for Field Effect Transistor

Extremely fast transistors with high levels of output power are needed to transmit microwave-frequency signals in wireless communications, radar and other applications. Silicon doesn't yield efficient and fast devices. GaAs yields fast transistors, but often without enough output power because of low breakdown voltages.

At the International Electron Devices Meeting (IEDM), researchers from Nitres Inc. (Goleta, Calif.) described very fast high-electron-mobility transistors (HEMTs) that offer both speed and power. These HEMTs were made from AlGaN/GaN layers grown on silicon carbide. In contrast to earlier efforts, they have a much higher aluminum content: more than 30% of the material composition is Al.

The Nitres team fabricated devices with 100 µm- and 150 µm-wide gates that dissipated up to 9.4 W/mm at 8.2 GHz. This is not only nine times greater than the best GaAs-based devices; it is the highest power density ever reported for a field effect transistor. One of the HEMTs — a large, 4 mm-wide device — dissipated up to 11.7 W at 8.2 GHz with 27% power-added efficiency. •


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