Who Will Gamble at 0.13µm?

Laura Peters, Senior Editor -- Semiconductor International, 1/1/2000

		At a Glance
	Semiconductor manufacturers must decide whether the risks associated with adopting 193 nm lithography, new capacitor materials and low-k dielectrics at 130 nm are worth the rewards.

The transition from 0.18 to 0.13 µm devices represents an enormous leap in semiconductor device performance that will take between two and three years to implement at leading-edge logic, memory and foundry fabs. By then, IC manufacturers will have made some very risky decisions regarding the number of tool platform and materials changes required to produce their devices. Attaining high device yields on chips with copper interconnect remains the greatest challenge for logic fabs today. The change to dual-damascene architectures from subtractive approaches is introducing new failure modes. Success in the CMP process for copper, interlevel dielectric and shallow trench isolation (STI) steps remains pivotal to producing high-yielding devices.

The following highlights the most critical changes likely to take place in the transition to the 0.13 µm (130 nm) device generation. These include modifications to the CMOS transistor structure and scenarios for copper and low-k dielectrics (Fig. 1, p. 54), DRAM capacitors, and requirements for system-on-a-chip devices.

130 nm lithography

Up until as little as three months ago, many semiconductor manufacturers were still projecting use of 193 nm lithography for critical mask levels in the 0.13 µm device. However, advances in 248 nm step-and-scan tools and associated processing, combined with a lack of maturity of 193 nm processes, are driving a migration to 248 nm lithography for all layers at the 130 nm node, according to John Cossins, U.S. strategic marketing manager at ASML (Tempe, Ariz.). "While 193 nm is certainly not yet excluded from the 130 nm node, the typical customer will use 248 nm step-and-scan tools and a combination of off-axis illumination, OPC, and, in some cases, attenuated phase shift masks," Cossins adds. He explains manufacturers must balance the inconvenience of introducing, for instance, PSM (phase shift masks) — with its more complex, costly reticles that are difficult to inspect — with the gain in process latitude it buys at a particular resolution. OPC (Optical Proximity Correction) will see extensive use at 130 nm due to process latitude benefits, he says.

The most critical lithography mask continues to be the gate CD. As noted in the 1999 SIA Technology Roadmap (Tables 1A, 1B), the 130 nm node designation refers to microprocessor and ASIC gates in the 85-90 nm range, which is relatively independent of the shrinking dimension of pitch between memory cells in DRAMs with a half-pitch of 130 nm.

The overlay budget continues to shrink with feature size. With a 40 nm overlay budget and a generally increasing number of metal layers (where overlay is more challenging to master), overlay capability has little room for error.

Gate formation

Shrinking channel length and thinning gate oxides push state-of-the-art etching capabilities. "At the gate level, maintaining CD across the wafer and being able to stop the etch on very thin oxide layers are the main challenges," says Jackie Seto, director of marketing for Lam Research Corp.'s (Fremont, Calif.) Etch Division. "To maintain gate oxide integrity, we use broadband interferometry to attain pre-endpoint and switch over to a very selective process." Dragen Podlesnik, general manager of silicon etch at Applied Materials, says poly and metal gate etch of sub-0.13 µm features must provide smaller critical dimension (CD) dispersion, extremely low CD microloading (the dimensional difference between dense and isolated features), plus the ability to tailor CD bias with techniques such as in situ resist trimming. In situ resist trimming refers to etching of the photoresist mask to shrink the CD. "Dual gate structures will place even greater demands on poly etchers, because n and p profiles will require precise matching and notch-free, undercut-free results," he adds.

In advanced microprocessor and communications devices, gate leakage current becomes critical for the reliability of ultrathin(<20Å) gate oxides. Many companies will implement new gate dielectric processes to decrease gate leakage. "Increasing the dielectric constant of the gate oxide by remote plasma nitridation provides lower effective oxide thickness," says Dr. J. Kelly Truman of Applied Materials' Transistor Gate and Capacitor Group. "A relatively simple addition to a clustered RTP chamber, remote plasma nitridation, can provide an order of magnitude reduction in leakage current over furnace-based gate oxide."

At the 130 nm node, the transition to alternative gate dielectrics represents "the most significant change in front-end-of-line processing we've seen in the last 20 years," says Scott Becker of FSI's Surface Conditioning Division. "Cleaning prior to depositing the new gate materials could lead to changes in prediffusion cleaning to become a combination of either HF last with an integrated rinse/dry using IPA or, alternatively, a reactive rinse using ozonated water and/or acidic rinses based on HCl, for instance." An integrated dry clean to control interfacial properties likely will be part of the gate cluster tool, making a strong argument for dry cleaning. "At 130 nm, the piranha clean is expected to be replaced by ozone/DI water cleans," Becker explains.

System-on-a-chip (SOC) applications including embedded memory require gate oxides of multiple thickness on the same chip. One approach, using high-current ion implantation of Ar and N species, allows oxides with multiple thickness to be grown simultaneously.

Memory cells

At 130 nm, some DRAM cell capacitors, particularly the stacked (rather than trench) design, will require new materials such as tantalum pentoxide or barium strontium titanate (replacing NO or ONO) as well as new electrode materials such as ruthenium, Ru, or platinum, Pt (replacing hemispherical grade silicon). Ta₂O₅ is the most viable new dielectric (with k > 25), though BST (k = 300) also is under consideration. According to Jim McKibben of Tegal (Petaluma, Calif.), major leaps in etcher design and process development are needed to get the right combination of physical and chemical reaction to etch these nonvolatile new dielectrics and metals. The SIA Roadmap calls for such dual-frequency approaches. Interestingly, the same dual-frequency etching approach that allows independent control of ion energy and ion density helps control profiles and rounding in the formation of shallow trench isolation (STI) structures.

Shallow trench isolation

Many companies made the transition from LOCOS to STI structures at the 0.18 µm node, but those that did not will certainly use STI at 0.13 µm. STI processes include anisotropic silicon etch, thermal oxidation, oxide fill and CMP. Bottom trench rounding is required for all STI schemes; top corner rounding is optional, depending on the subsequent deposition step. One of the most critical requirements for STI is the steep angle of incline made by the etch, which changed from ~86deg for 180 nm devices to 87-88deg for 130 nm devices, according to Seto, a dramatic change in terms of etching capability. Tools with the flexibility to perform hard mask open, etch, and top and bottom rounding in one process step also are becoming important.

Applied Materials sees the productivity benefits in the integration of the STI process, even as it continues to focus on performance, says Podlesnik. "For 0.18 micron spaces, CD control, vertical nitride and low profile and etch rate microloading will definitely help integration. You have to have good etch depth uniformity, for example, to get good oxide fill," he says.

STI CMP is the most critical CMP step due to the proximity to the device active region. In addition, companies typically have used expensive processes — either addition of a reverse mask step or dummy features — to deal with variations in pattern density. Applied Materials'Rob Davenport says reverse masks increase cost by about $20/wafer. CMP tool vendors have just recently introduced "direct" STI CMP processes to try to eliminate the extra mask step. In-line metrology to monitor CMP tool diagnostics such as pad wear, slurry flow control, slurry uniformity, etc., are becoming essential to CMP process control.

Shallow source/drains

The need to reduce transient enhanced diffusion (TED) with shrinking transistor dimensions drives the requirement for sub-keV ion implant processes capable of delivering production-worthy beam currents to form ultrashallow junctions. Though existing implanters are being stretched to their limits of capability, Aditya Agarwal, chief scientist at Eaton Corp.'s (Beverly, Mass.) Ion Implant Division, says, "Recent research shows that physical phenomenon such as sputtering-related dopant loss will most likely preclude the use of implant energies below 0.5 keV, regardless of available beam current."

Interestingly, the use of non-doping Ge implantation, N or Ar species might help attain the desired electrical characteristics by providing pre-amorphization or reducing junction diffusion. "Production-worthy Ge implant capability in the 5-30 keV range is extremely important," says David Duff, marketing director at Eaton. Though there's controversy over the importance of high ramp rate RTP processes on ultrashallow junction formation, "it is now clear that reducing the implant energy, annealing time and dose are of primary importance for achieving the shallowest junctions," says Agarwal. He adds that ultra-fast ramp rates (hundreds of degrees per second) are of secondary importance as current RTA tools are not capable of the same very fast ramp-down rates needed to significantly reduce the thermal budget further.

Applied Materials' Truman notes, "High RTP ramp rates are not sufficient to control junction depth. Optimal implant conditions — very low energy and high current — are a necessary starting point. 200-500 eV energies are a new frontier being implemented by many chip makers." He says the productivity challenge is to achieve beam currents > 1.2 mA, which requires a short beam line. "Uniformity during ramps, ramp-up and ramp-down rate, and absolute control of the spike temperature are all important factors."

Other critical implantation trends

Super-steep retrograde channel formation is being investigated using implantation of heavier, slower-diffusing Sb and In (instead of P and B, for n- and p-channel transistors, respectively). Indium implantation is particularly challenging, as the solid phase feed must be actively cooled when running other species. Energetic filtration prevents implantation of indium self-sputtered from beamline walls.

High-energy batch system ion implanters continue to deliver productivity advantages by providing not only high energy but also the low-tilt traditional medium-current implants. Leonard Rubin, scientist at Eaton, says the ability to chain implants together and perform sequential implants after loading a single batch of wafers once, increases throughput and results in smaller threshold voltage variations.

Buried layer implants ~2.5 mm below the silicon surface help to getter oxygen and metallic impurities from the device active region and can provide a low-cost alternative to epi wafers, particularly for 300 mm substrates. Retrograde triple wells, which first gained acceptance at the 0.18 µm node, are being more widely used in memory and logic devices while allowing independent optimization of different device types on a chip.

Salicides

TiSi₂-based self-aligned silicide (salicide) films will be replaced widely by CoSi₂ due to their lack of dependence on lateral dimension. At reduced feature sizes, TiSi₂ films inadequately transform from the high-resistivity C49 phase (70 mV-cm) to the lower-resistivity C54 phase (15 mV-cm). In the processing of CoSi₂ films, diode leakage issues must be minimized by annealing the cobalt or depositing it at high temperature (600degC).

Barrier metals and aluminum interconnects

The need to fill higher aspect ratio features with adequate step coverage drives a general transition from standard PVD to collimated or long-throw sputtering methods to ionized PVD and, eventually, metal CVD. Ionized plasma PVD was developed to extend the cost of ownership advantages of PVD versus CVD. The 0.13 µm node likely will see increasing adoption of ionized plasma technologies.

ILDs and low-k dielectrics

For various reasons, low-k dielectric use has been pushed out a few device generations. Originally considered a benefit at 0.25 µm and a must at 0.18 µm, it now appears 0.13 µm will see the first use of low-k materials withk<3.0. Integration issues involving the patterning, etching, polishing of the materials, and combining with existing aluminum, or, more commonly, new copper damascene processes, have been difficult to overcome. In addition, no ideal low-k candidate has been identified, with all materials fundamentally flawed in some respect.

The first implementation of materials with a dielectric constant below that of SiO₂ (k = 3.9-4.2) employed fluorine-doped SiO₂, or FSG, deposited by CVD, or HSQ (hydrogen silsesquioxane), a spin-on material. Both PECVD and HDP-CVD techniques can be used to deposit FSG films with k values in the 3.6 range, though the high-density plasma is able to extend k value to 3.3, according to Farhad Moghadam, VP and general manager of Applied Materials' Dielectric CVD Division. The most significant integration challenge with FSG involves properly stabilizing the film so it does not attack barrier layers. In general, FSG has so far received greater acceptance than HSQ, possibly due to moisture uptake and film cracking issues with HSQ. (See SI, Nov. 1999, p.56, for in-depth discussion of low-k integration challenges.)

True low-k begins, by most people's definitions, below 3.0. In the 2.5-2.7 range, carbon-doped oxide films (OSGs), offered by ASM (Tempe, Ariz.), Applied Materials and Novellus (San Jose, Calif.), offer the advantage of integration with other key processes by equipment manufacturers. The downside is a current lack of extendibility below a k of ~2.5 using the current trimethylsilane and dimethylsilane reagents, provided by Dow Corning (Midland, Mich.) and Schumacher (Carlsbad, Calif.). Batch-to-batch stability and uniformity of OSG also can be an issue.

Spin-on low-k materials are currently more extendible than CVD films to k < 2.0 for future device generations as porous versions of organic polymers, with lower k value based on pore volume, are being developed. The most integration work has been performed on two materials, SiLK from Dow Chemical (Midland, Mich.) and FLARE from AlliedSignal (Sunnyvale, Calif.). What has been lacking, until recently, is the integration capability of spin-on low-k dielectrics. Suppliers of materials, etch tool, CVD tools and track systems are forming partnerships to provide integration expertise to customers. "The SOD market really begins when CVD runs out of steam at k of 2.7," says Ajit Rode, general manager and senior VP of FSI's SOD group (Fremont, Calif.). The cornerstone of FSI's modular spin-on dielectric system is an in-line cure designed to provide stable low-k films with superior uniformity. The track design and environment are more than an extension of track systems for photoresist; they are dramatically modified systems designed to specifically fill the needs of low-k dielectric film delivery.

A crucial development that helps keep down effective dielectric constant of the film stack is the use of silicon carbide-based barrier layers that replace high-k silicon nitride (k = 7-9). Films such as Applied Materials'BLOk offer a k of ~5, higher etch selectivity than nitride and better adherence to FSG.

Because of all the combinations of options with low-k dielectrics and significant integration challenges, companies may push out the use of k = 2.5-2.7 films to the 0.10 µm generation. The timing for low-k use will depend on the absolute need for reduced line-to-line capacitance and necessary reduction in RC delay once the benefits of copper interconnects are maximized. "I believe if companies go with the materials they are using now, you'll see both inorganic CVD and spin-on organic films at the 0.13 µm generation," says Lam Research's Seto. "The bigger question is whether low-k materials will go into volume production at the 0.13 µm generation."

One integration challenge in dual-damascene is post-etch cleaning, due to the increased number of particle trapping sites with the structures' long canals and narrow vias. Both wet and dry cleaning techniques are being investigated for this yield-limiting step.

Cleaning companies are performing chemical compatibility studies with the variety of low-k materials "A group is trying to determine which existing and new cleaning chemistries are compatible with the dielectrics, so we can be poised to know which chemicals we can try based on the material," says FSI's Becker. New aqueous and semi-aqueous chemicals are continually being developed to address new types of residue removal (see December SI). "A lot of cleaning recipes following ashing previously used highly flammable solvents, but the new aqueous-based cleaners will enable us to link residue removal steps with traditional aqueous-based cleans for greater productivity," he adds.

"Chemical compatibility issues may eventually make wet stripping of photoresist too difficult," says Dr. Diana Ma, general manager of dielectric etch at Applied Materials. "Especially with ultra low-k dielectrics, solvent incompatibility may pressure development of new integration methods." New systems offer in situ integration for dual-damascene applications, with the main dielectric etch, dry photoresist strip and barrier removal done in the same chamber. "This was initially seen as a way to improve system throughput and cost efficiency. But now we're finding that an integrated dry process could become a necessity for consistent yield performance."

Copper interconnects

Though copper interconnects originally offered the promise of 30% faster devices with fewer metal levels and lower-cost production, few companies have attained such dramatic performance and economic advantages with copper. Surprisingly, for some companies "copper is actually more of a cost driver than a performance driver, making low-k the key enabler for high performance," says FSI's Rode.

Copper CMP is the most critical step in the copper interconnect flow. Figure 2 shows some of the failure modes. Problems of dishing and erosion plague the industry, similar to the issues in STI. "To deal with copper's topography issues, some people do intermediate oxide polishes, but that's extremely expensive," says Davenport of Applied Materials. "We are currently working on a non-selective approach to eliminate the topography, but at or beyond 0.13 µm, polishing with fixed abrasive pads may become necessary because it removes material from the high spots while there's no slurry to polish the low spots, resulting in excellent planarity and very low metal loss." Fixed abrasive pads, such as that offered by 3M (Austin, Texas), are a novel approach, however, and must displace the existing slurry processes that companies have worked so long to characterize and qualify.

In addition to the 3M approach, new fixed abrasive approaches are being pursued, according to John Aldeborgh, president of Ebara Technologies (Sacramento, Calif.). One uses a different medium and "so far indicates enhanced performance including improved planarization, decreased dishing and erosion issues, and a self-stopping feature, making it attractive for copper and STI CMP," he says. He adds that CMP tools capable of accommodating an increasing number of chemistries also are becoming essential for copper and other CMP applications.