Roadmap Emphasizes Co-Design Challenge
John Baliga, Associate Editor -- Semiconductor International, 1/1/2000
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One of the five near-term "Difficult Challenges" is the development of "Coordinated design tools and simulators to address chip, package and substrate complexity." On the subject of co-design, the Roadmap states: "Packaging must perform more than a protective function. It must satisfy the ever-increasing need for performance, high reliability, thermal, and power management at an affordable cost. Packaging design tradeoffs can no longer be made independently of the chip and system; they must be considered concurrently in a system-level approach so as to minimize suboptimization."
Three near-term challenges deal with flip-chip interconnection. One is to develop bump and underfill technology compatible with the copper interconnects and low-k dielectrics on the chip. Another is to improve underfills, with calls for better manufacturability, reliability to 170°C for automotive applications and comprehensive parametric knowledge of all the involved components in flip-chip attach. The third is to improve organic substrates for compatibility with lead-free solders (high Tg), low dielectric constant (k 2.0), lower CTE ( 6.0×10-6/K), lower moisture absorption and improved area array escape wireability.
The final near-term challenge is cooling for cost-performance and high-performance devices. The goals are to get junction temperatures down to 40°C above ambient and to delocalize power density on the chip.
There are three new sections: system-on-a-chip packaging, wafer-level packaging and flip-chip electromigration. It noted that packaging a system on a chip actually would be simpler than packaging component ICs when die sizes are determined by the I/O pads. In other cases, a system in a package would be preferred. The wafer-level packaging section underscored the need for fan-in of interconnects to maintain a constant interface through die shrinks. The electromigration limitations of lead/tin solders are dealt with in a straight-forward manner, giving a table of the current limits per bump as a function of pad size and temperature. The electromigration limits together with power and ground needs will determine the number of I/Os for a device.
"System-level view of integrated chip, package, and substrate needs" is given as a difficult challenge in the long term, beyond 2005. Ultra-high-frequency capabilities for designing high-density digital and mixed-signal packages is another. Closing the gap between chip and substrate technologies, and the manufacturability and reliability of large body packages round out the long-term challenges.
In the upcoming years, packaging will be viewed as part of the "interconnect continuum," in which the needs of the system are optimized rather than the needs of individual components. The message the Roadmap seems to be sending is that optimizing the chip, package and board separately will be "suboptimal" in upcoming systems. •
| Editorial Comment | |
| Over
the past couple years, I have drawn particular attention to three emerging
trends in the packaging side of the industry: the need for increased
collaboration among chip, package and board makers; the need for sensible
CSP standards; and three-dimensional packaging. These three seemingly
separate concepts are actually strongly connected.
I have been an advocate of three-dimensional interconnection to some degree, and I think area array interconnection of multiple dice will not only take place, but come into the mainstream very soon. There is one problem with the industry pursuing this direction, though. The packaging industry will not be ready for 3-D packaging until it proves it can bring sufficient order to something that is simpler: area array chip-scale packages. Note that I say the industry will not be ready; the technology is here. Even without the 3-D prospect, simplified area array standards for both CSPs and flip-chip attachment are needed to give test socket makers and other suppliers a simpler set of goals. I have done what I can to promote the Lego-block scheme that Joe Fjelstad, now with Pacific Consultants (Mountain View, Calif.), has been promoting for years: that a 0.5 mm grid and its depopulated versions be the accepted standard for area array pitches. The reasoning goes like this: When you look at what it takes on the circuit board to route I/Os away from an IC, there is really only a need to have one ball pitch between 1.0 and 0.5 mm. Why not use a 50% depopulated 0.5 mm pitch? That gives a 0.707 mm pitch without having to create another grid. The key phrase in this reasoning is "when you look at what it takes on the circuit board." This is where collaboration between chip, package and board makers comes in. As these three technology areas continue to merge, approaches that optimize overall manufacturing effectiveness will become much more useful than approaches that optimize each separately. If the three technology areas are going to come together, they might as well be harmonious. In December 1998, I stated that packaging technology would mutate in the upcoming years, and that chip-scale packaging was merely the first of the mutations. I continue to stand behind those words, and I hope the necessary commitment to instilling order materializes before the next wave rolls in. • |
To contact Joe Fjelstad by e-mail: joef@pacificconsultants.com
SIA 1999 Roadmap http://public.itrs.net
