Chip-Package Codesign: Capabilities Improving, Need Growing

The last few editions of the International Technology Roadmap for Semiconductors (ITRS) have called for the development and improvement of chip-package-board codesign capabilities. Faster, more complex chips with ever-increasing numbers of I/Os and power connections drive this need, as well as the increasing number of systems-in-package (SiPs). Some surprising cost factors are also driving codesign.

Earlier this year, Taiwan Semiconductor Manufacturing Co. (TSMC, Hsinchu), an IC foundry, released version 5.0 of its reference design flow. It includes capabilities for integrating the design of the chip and package, using tools from various companies, including Cadence (San Jose) and Optimal Corp. (San Jose). Timing and substrate routing challenges were among the reasons given for doing this, but the primary reasons were I/O and power planning.

Low-power, high-performance designs are increasing. In the 90 nm process realm, chips are designed with supply voltages as low as 1 V. At this level, even the IR drops in the package's power planes must be factored into the chip design. Designing the package's power planes to closely match the chip's needs can also reduce wasted power and increase battery life. These things can only be done when the chip and package are designed concurrently.

Many times, chipmakers design SiPs with a concurrent approach, because they usually view SiPs much like systems-on-a-chip (SoCs). Drive circuitry on the component chips is sized to suit the short chip-to-chip distances while being efficient with power consumption. In some cases, the package wiring is used as an extension of the on-chip wiring. For example, moving global clock and power distribution onto the package can reduce clock skew and reduce die sizes.¹ Optimizations like these are rare now, but they will have to be performed more often in the upcoming years.

With or without power quality and cost constraints, timing is getting trickier. Signals sent at the same time can reach their respective I/O pads at slightly different times, and that difference can be significant compared with today's short clock cycle times. Codesign can allow designers to use the package to compensate for these differences.

In a typical case, like a flip-chip BGA, the task of matching the chip's I/O pads to those of the package substrate is straightforward. Tossing the IC design "over the wall" to the package designer still works in many of these cases, and it is still done this way most of the time. Usually, the worst that can happen is the package ends up with more wiring layers than necessary. In an increasing number of cases, the package is more expensive than the die. Chip-package codesign is done in these cases to minimize cost by minimizing the number of layers in the package substrate. Minimizing package layers can also help with power delivery.

Currently, concurrent design is usually done in stove-pipe fashion. Tools are now available to perform chip-package-board codesign in a top-down fashion.

Cadence has proposed what it calls the virtual system interconnect model for electronic system design. In it, the overall system interconnect is modeled first. Chip, package and board designs are then adjusted to fit the specifications of the interconnect model. The company offers capabilities for this design flow in its Allegro suite.

It is not necessary for all chips, packages and boards in a system to be designed from scratch in every system design. In the case of a die shrink, for example, the chip is the only thing that needs to be redesigned. However, that chip should be designed in a codesign context to address power, timing and package layout challenges.

Mentor Graphics (Wilsonville, Ore.) recently announced its I/O designer product for codesigning FPGAs and their circuit boards. FPGAs are widely used in cases calling for moderate product volumes, and they can be rather complex, with multiple I/O formats and as many as 1500 pins. There are usually many ways to configure a set of FPGAs to perform the same logical functions. An I/O designer helps to choose the configuration that optimizes the overall system in terms of cost, performance and manufacturability. The company is examining further options with regard to concurrent design.

Interconnection is starting to determine the cost and performance of electronic systems at every level: on the chip, in the package, and on the board. Prototyping will become much more costly at every level in the system. Design approaches that model all of the interconnection in a system with high granularity and visibility will be necessary as chip complexity and I/O counts continue to increase.

For additional information on semiconductor packaging, go to www.semiconductor.net/packaging