WLP – Promises and Pitfalls

Wafer-level packaging (WLP) has captured and held the imagination of the IC packaging community for more than a decade. Most WLP developers appear to have drawn inspiration from redistribution wired flip-chip technology used in IBM's famed C4 process and dating back to the 1960s. One notable exception was M-Pulse (later ChipScale Inc.), where leads were moved to the periphery and wrapped around the edges of the die by some clever processing methods in the 1991 time frame. Since then, there have been numerous variations on the general theme coming from national, corporate and university laboratories around the globe. A search of the U.S. Patent Office records using the term "wafer-level package" returns ~90 issued and >100 pending patents. However, due to the vagaries of patent writing and phrasing, the number of patents could be a few to several times larger. Many patents are also being written in support of wafer-level processing and do not directly describe the package itself. The reasons for the attraction of WLP are many. Among the most alluring are low cost, small size, high performance and shortened manufacturing cycles and time to market. While there continue to be differences in opinions as to what exactly constitutes an IC package (e.g., some count redistributed wiring flip-chip as a wafer-level package, while others insist that a wafer-level package must include greater physical protection and be subject to standards to be counted as a package), common ground and agreement have been found in the basic premise that the finished device should be mountable using standard surface-mount assembly techniques. Semantic arguments aside, WLP is still an important option for device packaging.

To date, most of wafer level's promises have been delivered in the form of devices with few I/Os (2-24) that have a relatively small size, but are large enough to place the I/O at a pitch that can be assembled to a PCB at high yield. Diodes, transistors and small logic devices have made the greatest use of the technology, and cellular phones have been a major beneficiary. Efforts to adapt the technology to what would appear to be attractive markets such as memory have been stymied, at least in part, by the fact that chips from different manufacturers are often of different sizes, making the chore of mixing memory devices from different suppliers and uniform assembly a daunting task.

Wafer yield is also a consideration that must be carefully accounted for. In the act of WLP, by definition, all devices on the wafer are packaged at once; thus, the bad chips are packaged alongside the good, making for some measure of wasted effort. Likewise, there is concern for the yield of the packaging process during which a bad package could be formed on a good die, making the assembly useless. Clearly, a sharp pencil must be used when doing a financial analysis of implementing a potential WLP solution.

One must also consider the matter of test. To capture the full benefit of the WLP option, testing should ideally be performed while the completed assembly is in wafer form. Depending on I/O count and pitch, this can be a significant challenge. A number of companies, both new and established, are working diligently to develop the test solutions that will be needed to make the transition to broader use of WLP technology.

There is no clear consensus yet as to the limits of WLP; some suggest that it will remain a technology reserved for low-I/O devices, while others believe in the technology's promise as a solution for even high-end processors. For example, chip-scale packaging pioneer Tessera first proposed a WLP almost a decade ago, wherein function was shared between chip and package (e.g., power, ground and cross-chip circuit routes are provided for in the thicker metals of package rather than on the chip). In such a paradigm, the IC chip could only be tested when the entire packaging assembly was complete. A key requirement for this to work is a stress-decoupling layer placed between the package and IC to compensate for the large CTE difference. This is actually a constant concern for nearly all IC packages with chips having more than a few I/O.

In summary, WLP is a technology of continuing promise and one that is likely to see an expanding role in the future because of its many benefits. However, there are still risks to be considered. The current rate of innovation will no doubt yield some solutions designed to limit those concerns, but the reality and risk of post-processing an entire wafer at once will never go completely away if one takes the WLP option.