These Aren't Your Father's Transistors!

With the prospect of nanotransistors becoming an everyday reality, there seems to be insufficient industry concern over the statistical significance of measurements that device manufacturers will have to perform to maintain process control.
 
Consider a local measurement done on part of the die by a process engineer who wants to control a CD there. Something he really needs to know is the average and distribution of the measurement being taken — on a bell curve, for instance, the average value and curve's width. If the average value were perfect, but the distribution extremely wide, the result would be very small numbers describing the linewidth of interest. This does not happen if the measurement only provides an average. If this measurement is only one piece of the distribution, one value, then there is even less data.

For device makers to cope with the stringent requirements they will face with these much smaller features, they must think both at the local level, across the die and across the wafer, and determine whether a measurement provides sufficient statistical significance for the factor they are trying to control.

To get there requires more from measurements, shifting them from the scribe line to the actual die. We must consider what the measurement provides — does it give an average value? If so, is that what is required for process control? Are sufficient values being taken across the wafer to determine if the variation goes across it? As we move toward increasingly smaller devices, the divide between physical measurements and the electrical values that must be controlled is widening. Just as there is design for test, we may have to look to design for measurement.

AFM image of IV-VI semiconductor quantum dots. Two monolayers of PbSe were grown on 2 µm PbTe(111) using MBE. The lattice mismatch of -5.5% of both materials leads to the formation of nanosized, self-assembled islands once a 1.5-monolayer coverage is exceeded. The wetting layer, showing the monolayer surface steps, and the 3-D islands, which are ~150 Å in height, are clearly resolved by the AFM. (Source: M. Pinczolits, Institute of Physics, University of Lintz and American Institute of Physics)

Manufacturers have little experience with advanced devices such as short-channel transistors. They know there is a difference between short- and long-channel transistors, but do not yet know what is needed for process control. This results from a lack of communication between engineers doing this advanced work and those designing and producing metrology platforms. Standards and measurement tools are needed that will be up to the task.

Double-gate structure transistors, finFETs, are coming into line. To control the thickness of the dielectrics on finFET sidewalls, manufactuers are looking at a vertical, rather than horizontal, measurement plane. It is the same complication faced with trenches, where one needs to control the sidewall, but can really only measure on the flat bottom area. Thus, the control that can be exerted on the horizontal features becomes increasingly tenuous on the sidewall. Presently, workarounds exist for the fabrication of these features, but what happens when the tolerances on the sidewall dielectric thickness become truly infinitesimal is anyone's guess.

Test and measurement done during wafer processing must migrate to a testable area in the kerf between the die, or some small area on the die, which will enable electrical test to be done quickly and provide the necessary information. The industry has never been too inclined to electrically probe the wafer until it has gone all the way through. There is a justifiable aversion to putting down a contact on the wafer, because the measurement can sacrifice the die it is done on and add throughput complications. Present test equipment may not be up to this procedure, and other resources, such as nanoprobes, may be needed to find the area where the electrical test is to be done. One goal for this capability is to become non-contaminating and non-destructive.

A better understanding about what these devices are going to be like will determine what must be measured to enable variation control. This information must be processed to determine the kind of metrology tools and process control that will be needed, leading to added AEC/APC, where a smart software system that takes the data that results from the physical measurement and tracks the process and maintains it, tweaking the tool if necessary, to ensure that the chip's electrical properties will turn out well.

But this requires even closer work between OEMs and academia, particularly those researchers who are experimenting with nanotransistors. Simulation and modeling work is needed on what the effect of manufacturing variation has on the transistor's properties as well those of the whole chip. This would map a course clarifying which parameters must be controlled then, besides those being managed with existing transistors.

For additional information on inspection, measurement and test, go to www.semiconductor.net/imt