Unavoidable Variations: Coping at the Design Level

It's common knowledge that, as the complexity of the semiconductor manufacturing process increases and new materials are introduced, it's likely that process variations will be more difficult to control. Engineers have been talking about zeroing in on acceptable process windows for years, and have been successful in doing so. But those days may be over.

In many cases, it is now almost impossible for designers to accurately predict what will be printed on the wafer, particularly when reticle enhancement techniques (RETs) such as optical proximity correction and phase-shift masks are used. There is simply not very good correlation to the geometries printed with these technologies and the fairly rudimentary design rule checking (DRC) programs that designers use. All the big EDA companies are working aggressively to correct this problem, but it's not yet clear who will need to take ownership: Designers? Maskmakers? Manufacturers? A collaborative effort will almost certainly be required.

But handling RET issues may be only the tip of the iceberg. As we report in this month's cover story on copper CMP, there are an incredible number of variables that must be considered during CMP, all of which make large process variations all but unavoidable.

First, consider the CMP variables found in the incoming wafers (differences in grain size, thickness uniformity of the copper across the wafer and underlying topography). The integration of low-k adds another degree of complexity (mechanical strength, porosity, existence of capping or pore-sealing layers, etc.).

Then, consider the mechanical and chemical components of CMP. Mechanical components include the downforce applied to the wafer and the types of abrasives in the slurry. And there are new abrasive-free slurries that substitute "hard" abrasives with high molecular weight polymers.

Finally, one has to consider pattern dependency effects, since narrow lines in dense arrays will polish quite differently than large lines in open features. Manufacturers compensate for this by adding dummy fill features, which, of course, add even more variables.

I'm sure CMP technologists relish the opportunity to keep all of these variables under tight control. But try as they might, there are increasingly cases where there is, for example, too much copper loss on a given line, which means that line can't carry as much current as the designer intended. Not only does this mean the design might not work, but it can create a nightmare in trying to find out why it doesn't work.

The good news is that there are a whole lot of people and companies working on ways for designers to anticipate the process variations — such as the implications of RETs or the pattern dependencies encountered during CMP — during the design phase, before they commit to producing a $1M mask set that may or may not work.

"As we move forward into the smaller geometries, process variations are going to continually push the requirement for the designer to know more about the manufacturing process," said Taber Smith, president of a company called Praegasus that is selling characterization wafers and evaluation software that does exactly that.

This will all be great for the designers, who I suspect will sit in their comfy chairs and push a button to run a program called "DRC Plus" or some such thing. But what's in it for the manufacturing folks? Plenty, says Taber: "One of the things we do when we go in to talk to a manufacturer is to show them all the kinds of things they can do to improve the process using modeling technology. For example, in many cases, they can actually screen the designs coming in, and can hand back those that need some adjustments in specific locations. It can also be used for process improvement." I can almost envision the day when process variations can be so easily accommodated during the design phase that manufacturing guys can actually relax — well, relax the process specifications anyway.