RTP-Grown Oxynitride Layers Meet Gate Challenges

Information technology's progress over the past decades has depended on the SiO₂/Si system's extremely high quality. One key application of this system is MOSFET gate dielectric. Until now, SiO₂ gate oxide played a critical role in device performance.¹ As lateral MOSFET dimensions scale into the deep submicron regime (<100 nm), SiO₂-based gate dielectrics are reaching their limits.
 
According to the 2003 International Technology Roadmap for Semiconductors, the 100 nm technology node requires the gate dielectric's equivalent oxide thickness (EOT) to have values of 0.9-1.4 nm for low-operating-power ASIC MOSFET devices. Direct tunneling currents through the SiO₂ gate oxide increase exponentially with decreasing oxide thickness. Another drawback related to gate dielectric thickness downscaling is the degradation of its barrier properties against the diffusion of dopants from heavily doped p+ polysilicon gates (boron penetration).

High-k gate dielectric materials like Al₂O₃, HfO₂ or nanolaminates of different alloys may be the mid-term solution; however, their integration into the existing process flow is a challenge. Most high-k materials also need a robust interfacial layer to improve the silicon/high-k interface properties.

Ultrathin nitrides/oxynitrides can serve as a dielectric solution and/or as an interfacial layer for high-k dielectrics for future nodes. Common methods for forming the nitride/oxynitride layers have been CVD-nitride deposition with sequential post-nitridation anneals (PNAs) in oxygen-containing gas ambients, rapid thermal oxynitridation in NO or N₂O, plasma nitridation followed by a PNA in oxygen, or rapid thermal nitridation (RTN) of thin oxides in NH₃. However, these approaches seem to encounter scalability problems for sub-90 nm technology nodes.

Conversely, little work has been done using NH₃ in RTN of silicon to form Si₃ N₄. Here, we present the properties of ultrathin silicon nitride/oxynitride layers prepared by RTN of silicon in NH₃ followed by PNA in oxygen and in steam. Prior to the nitridation, a native oxide reduction process was carried out to ensure a well defined starting growth front with no or controlled SiO₂.

Both nitride and oxynitride layers show excellent barrier properties, including significantly lower tunneling current compared with SiO₂ of identical EOT. The interface properties are sensitive to PNA processing. For an optimized PNA with steam and subsequent forming gas treatment, the interface trap density (D_it) of the thermally grown SiON layer is better than that of a dry thermally grown SiO₂ layer (D_it ~10¹¹ eV^-1cm^-2). We will compare tunnel current densities as a function of EOT (measured at -1 V) with other dielectrics, such as RTP SiO₂, LPCVD oxynitrides and Al₂ O₃. For the same EOT, the tunnel current density of the thermally grown nitride/oxynitride layers were about four orders of magnitude lower than that of SiO₂.

A key to successfully growing ultrathin nitride layers on silicon wafers is starting with a well defined surface. Usually, the silicon surface is covered with native SiO₂. Although it can be removed by wet chemical cleaning — diluted HF — spontaneous silicon surface re-oxidation after cleaning and before nitride growth is unavoidable. Furthermore, wet chemistry may introduce contaminants onto the silicon surface that can deteriorate the subsequently grown nitride layer's quality. There is a need for an in situ pre-nitridation cleaning process that reduces or, ideally, removes the wafer's native oxide inside the growth chamber immediately before the nitridation process starts.

According to the growth/etch model of Eisele et al.,² at elevated temperatures there is a non-negligible diffusion of bulk silicon into the overlaying SiO₂ layer. For thin oxides — 12 Å native SiO₂ — this diffusion transports silicon atoms to the SiO₂/ambient interface, leading to the following reactions:

Si(s) + O₂(g) → SiO₂(s)      (1)

Si(s) + SiO₂(s) → 2SiO(g)      (2)

Reaction 1 describes the SiO₂ layer's growth on the silicon wafer in an oxygen-containing ambient, whereas Reaction 2 describes SiO₂'s conversion into volatile SiO in oxygen-free ambients — a pure argon ambient. Because of its high vapor pressure at elevated temperatures (900°C or above), SiO desorbs from the wafer's surface. In this way, the native SiO₂ layer can be reduced or completely removed. Immediately after this cleaning process, nitride formation can be initiated without unloading the wafer from the growth chamber.

The wafer's atomic surface roughness quality after the in situ cleaning process is an important parameter that may influence subsequent nitride/oxynitride growth and the ultrathin dielectric layer's electrical properties. Therefore, surface quality investigations on 200 mm wafers before and after the in situ cleaning process have been carried out. Wafers, p-type with a <100> orientation and native oxide of 12 Å, were processed in a Mattson 3000 RTP tool with pure argon at >900°C for 30 seconds.

Before and after the cleaning process, the wafers' haze level was found to be unchanged, with a mean value of <0.1 ppm (measured on a KLA-Tencor SP1 haze and particle measurement tool). This indicates that the cleaning process does not deteriorate the wafer's surface. The actual amount of native SiO₂ removed by this in situ cleaning process is still under investigation. Ex situ atmospheric ellipsometry measurements, carried out about two minutes after the process, indicated that, at most, two monolayers of native oxide were left on the silicon surface.

The common methods for forming ultrathin nitride/oxynitride layers have been CVD-nitride deposition or plasma nitridation (PN) of ultrathin SiO₂, both followed by post-nitridation anneals in oxygen-containing gas ambients. Thermal oxynitridation in NO or N₂ O and RTN of thin oxides in NH₃ has also been widely applied. Here, the nitride growth was done by using NH₃ + Ar as ambient in RTN. The nitride growth was carried out immediately after the in situ cleaning process in the same RTP chamber.

For optimizing the NH₃ concentration, nitrides with EOT ~13 Å were grown with the concentration of NH₃ in argon varied between 3, 10 and 100%. The growth temperature initially chosen was 1100°C. For the growth of nitrides with smaller EOTs, such as 10 Å or below, a growth temperature of ~900°C in a 60-second period was used.

The nitride layers' surface quality was first investigated with atomic force microscopy. An area scan of 1 × 1 µm showed that typical surface roughness of an as-grown nitride surface was <0.5 Å RMS. Results indicate that the nitride surfaces were atomically flat, and no abnormal surface roughness was observed.

The electrical quality of these nitride layers grown with different NH₃ concentrations was examined by C-V, G-V and I-V measurements on MOS capacitor structures with a 160 µm diameter and a thermally evaporated aluminum gate. Usually, aluminum gate is not used on thin dielectric because of spike formation. However, here the oxynitride layers were found to have such good barrier quality that no spike formation was observed. An aluminum gate was thus used in this work. From these data, the interface state density was extracted by using the conductance method,³ and the tunneling current density (j at V_G - V_FB = -1V, where V_G is the gate voltage and V_FB the flatband voltage) was also obtained.

In Figure 1 , the tunneling current density and the interface state density (D_it) of the nitride layers are shown as a function of NH₃ concentration. Both the tunneling current and D_it vary with the NH₃ concentration in argon. With 10% NH₃, the tunneling current and D_it show a minimum of 0.02 A/cm² and 2.5 × 10¹³eV^-1 cm^-2, respectively. This tunneling current is impressively low and has a value of about two orders of magnitude lower than that of a typical 13 Å-thick SiO₂. However, the D_it value is much higher than that of typical SiO₂ layers and therefore not very satisfactory.

1. These graphs show the tunneling current density (left) and the interface state density (right) as a function of the concentration of NH3 in argon during rapid thermal nitridation for nitrides grown at 1100°C.

Because of the substitution of O atoms by N atoms,^4,5 as-grown Si₃ N₄ layers on SiO₂/Si surfaces contain dangling bonds. These cause bandgap energy states that trap an electron or a hole, depending on the Fermi energy level. Thus, due to gap states, the interface state density of an as-grown Si₃N₄ layer is expected to be high. This partly explains the large D_it values of as-grown nitride layers. Even if the nitride/silicon interface was free from native SiO₂, SiN_x bonds still exist at the Si₃N₄/Si interface. SiN_x bonds also have a dangling bond that traps charge carriers, leading to interface defect. The high-defect interface state density of the as-grown nitride layer can be reduced by passivating the gap state through post-nitridation anneal and/or H₂ termination.

Nitride layers with 13 Å geometric thickness grown with 10% NH₃ in argon were post-annealed in pure oxygen or water (steam) ambients. Anneal temperature for the oxygen processes was 1100°C, which resulted in SiON layers with an EOT of ~15 Å. The process temperature was 1000°C for the post anneals with steam, such that EOTs of ~18 Å were obtained. After aluminum dot deposition for electrical measurements, one wafer with PNA in steam was further annealed for 30 minutes at 450°C in forming gas ambient. The D_it values of the layers after oxygen PNA, steam PNA and steam PNA plus forming gas treatments were respectively determined (Fig. 2 ). All post anneals helped to further reduce interface state density. This can be explained by the passivation of dangling bonds with oxidants. However, steam PNA led to a stronger D_it reduction than oxygen PNA. After the steam PNA, a D_it as low as 6 × 10¹¹eV^-1cm^-2 was obtained.

2. Dit of nitride layers grown with 10% NH3 in argon at 1100°C after different post-nitridation anneal (PNA) processes. As reference, the Dit of as-grown nitride layer is also shown. Typical Dit level of SiO2 is 1012 eV-1cm-2.

Interestingly, PNA in steam followed by a forming gas treatment further lowered the value to 10¹¹eV^-1cm^-2. These D_it values were two orders of magnitude lower than that of the as-grown layer. This extreme reduction of D_it may be caused by an H₂ passivation of the dangling bonds. The tunneling current of the nitride layers after steam PNA, with or without forming gas treatment, was also reduced into the 10^-5 A/cm² regime, more than five orders of magnitude lower than that of an SiO₂ layer with the same thickness (Fig. 3 ).

3. Tunneling current density as a function of EOT for dielectric layers grown by different technologies.

All tunneling currents of oxynitrides lay between that of SiO₂ and Al₂O₃, where SiO₂ layers form the upper limit and Al₂ O₃ layers form the lower limit. In the range of 10-20 Å EOT, RTP-grown oxynitrides followed by PNA with steam achieved extremely low tunneling currents. LPCVD-grown oxynitrides followed by N₂O RTP show tunneling currents lying between SiO₂ and NH₃ RTP technologies. Thus, RTP-grown oxynitrides followed by PNA with steam are good candidates for gate dielectric formation for the 100 nm technology node and below.

The nitrogen profile may also influence the physical properties of the thin nitride layer (e.g., j).⁶ Therefore, SIMS measurements were also carried out on the layers. In Figure 4 , the SIMS profile of a typical nitride layer grown with the process 900°C/60 sec/10% NH₃ (argon cleaning used) is shown. The sputter source was oxygen ions with an energy of 250 eV at 70°C from normal incidence,⁷ the measured signal was Si₂ N (Fig. 4 ).

4. Nitrogen-depth profile measured by SIMS (source: O2, 250 eV, 70°C) for an SiON layer grown by the processes 900°C/60 sec/10% NH3 (argon cleaning used) and post annealed in steam. This measurement was carried out by FEI Co. (Munich, Germany).

Concentration calibration was performed by a relative sensitivity factor (RSF) procedure. The RSF of Si₂ N/Si₂O was determined by a quantified standard.⁸ A steep decay at the dielectric/silicon interface (~1.6 nm) is evident. The oxynitride layer's nitrogen profile appears homogeneous throughout. This homogeneous structure is believed to be more advantageous than the usual SiON/SiO₂/Si dielectric structure, resulting in a lower tunneling current.⁸

Results show that oxynitride grown with RTP in NH₃ is a suitable candidate for gate dielectrics for the 100 and/or 90 nm technology nodes. However, for the 65 nm technology node, the gate dielectric material should have an even higher k, a smaller thickness and reasonably low tunneling current. One approach is to increase the oxynitride dielectric's nitrogen content and simultaneously reduce dielectric thickness. This is particularly difficult to achieve with the popular PN method; a parasitic reoxidation of the silicon/dielectric interface in PN limits the dielectric thickness' downscaling with high nitrogen content below 15 Å EOT.⁹

However, downscaling thickness and increasing nitrogen content in NH₃ RTP-grown oxynitrides is easily achieved by varying nitridation temperature and/or adjusting post-nitridation annealing. We annealed oxynitride layers with identical physical nitride thickness with different post-nitridation oxidation conditions. In Figure 5 , the EOT of these oxynitride layers measured by Quantox are plotted as a function of their nitrogen content. Oxynitride layers with <10 Å thicknesses and nitrogen content as high as 28% can be achieved. The nitridation condition for this ultrathin oxynitride was only 900°C for 60 seconds. RTP nitridation has the advantage that layer thickness downscaling is accompanied by thermal budget reduction.

5. EOT against nitrogen content of oxynitride layers with identical physical nitride thickness but annealed under various post-nitridation oxidation conditions. The EOTs were measured by Quantox, and the nitrogen content was estimated by XPS.

These RTP oxynitride layers were applied to NMOS structures as gate dielectric material for tunneling current investigation. The tunneling currents of the RTP and PN gate, oxynitrides in NMOS, were comparable for the 12-15 nm EOT regime; however, in the <10 nm EOT regime, the RTP oxynitride's gate tunneling current was slightly higher. This is still in good agreement with the predicted tunneling current, estimated by extrapolating tunneling currents in the 12-15 nm EOT regime to the <10 nm EOT regime (Fig. 6 ). It was also observed that the oxynitride layer's nitrogen content influences channel mobility of the NMOS transistor. By varying the nitrogen concentration and the nitrogen profile, channel mobility is optimized.

6. Tunneling current density measured on NMOS structures as a function of EOTs for oxynitride layers grown by NH3 RTP followed by PNA. As reference, tunneling current density of oxynitride layers formed by PN are also shown.

The ultrathin oxynitride layer's high tunneling current may still have to be minimized by process optimizations before oxynitride is introduced into 65 nm technology; however, oxynitride may find application in new gate dielectric concepts, such as in the use of high-k gate dielectric materials like Al₂O₃ or HfO₂ or nanolaminates of different alloys.

High-k gate dielectric materials have extraordinarily low tunneling currents and impressively high dielectric constants. However, most need an interfacial layer to improve the silicon/high-k interface properties. This should be a thin dielectric with a reasonably high k. The interfacial layer commonly used is SiO₂;¹⁰ however, its use has a major disadvantage: Most high-k dielectrics must be deposed in oxygen-containing ambients or annealed with oxygen gas after deposition. Unfortunately, this leads to further growth of the SiO₂ interfacial layer. This subsequently results in an increase in the gate stack's EOT.

A more elegant alternative to SiO₂ as an interfacial layer will be post-oxidized NH₃ RTP-grown silicon oxynitride. This interfacial layer could have an EOT of 9 Å and a nitrogen content of 28% or higher. This oxynitride interfacial layer combines the advantage of small thickness and a large enough k value, caused by high nitrogen content. Furthermore, the layer's high nitrogen content bars further oxidation, keeping the interfacial layer's EOT unchanged during high-k dielectric formation processes.

RTP-grown oxynitride layers with NH₃ followed by PNA show impressively low tunneling currents and low interface state densities. These properties indicate that these are good gate dielectric candidates for the 100 and 90 nm technology nodes and real alternatives to current LPCVD and PN growth techniques. In the more advanced 65 nm technology regime, an ultrathin NH₃ RTP-grown oxynitride layer, because of its high nitrogen content, may also serve as the interfacial layer between the high-k gate dielectric and the silicon surface.