Sony Evaluates and Eradicates Plasma Damage

Optimization of dielectric etching processes for dual damascene are normally centered around obtaining optimal aspect ratios, profiles, etch rates and etch stop characteristics. However, interconnects also require proper interfaces between the low-k dielectric, barrier materials and the copper, which, to a degree, depends on plasma damage. Therefore, etching and ashing processes must produce as little plasma damage as possible to improve yield and reliability.

In a recent study, engineers from the Semiconductor Technology Development Group (SSNC) of Sony Corp. (Kanagawa, Japan) and Sony Computer Entertainment Inc. (Nagasaki, Japan) demonstrated the degradation of interconnect reliability caused by plasma damage, showed ways of quantifying plasma degradation at the bottoms of via holes, correlated low-k damage with reliability, and developed plasma control techniques for 90 nm device production. They concluded that precise control over plasma-surface interactions is essential today, and will become more important with next-generation devices.

The group determined that excess CF_x radicals degraded copper quality. The concentration of these radical species is a function of partial pressure and dissociation of fluorocarbon gases in the plasma.

The test structure included two copper layers, used a tantalum barrier and copper seed, low-k (SiOCH, k=3.0), dielectric barrier (k=5.0) and a copper M1 trench in SiO₂. The copper was deposited by ECP, followed by CMP, and an organic acid treatment, followed by time-of-flight secondary ion mass spectroscopy analysis, which showed organic acid removed compounds such as CuC₆H₅.

When copper has been purified with organic acid, it is more susceptible to plasma damage from the SiC etch stop, leading to excess polymer in vias. Using tools including mass spectroscopy, a plasma absorption probe and optical emission spectroscopy (OES), the group was able to evaluate the amount of CF_x radical, plasma density and dissociation degree of C-F and O₂ molecules in various plasmas. When the dissociation rate (electron density) was increased, the copper surface degraded (Fig. 1 ). Lower O₂:fluorocarbon flow rate in the plasma generated excess polymer on the copper. On the other hand, higher O₂:fluorocarbon flow did not generate polymer on the surface, but oxidized the copper. The optimal dissociation rate and balance of O₂:fluorocarbon preserved copper surface integrity. Prior variations in wafer-to-wafer and lot-to-lot yield were remedied, and high via resistance was reduced from 16% in 26 lots to 5% in 40 lots, with the adjustments.

1. With high power and low O2 flow rate (a), an ion-assisted reaction produces excess CFx radicals. The optimized plasma flux (b) involves a spontaneous surface reaction at low power and high O2 flow rate.

Next, the ashing process was optimized to reduce electromigration failures. The engineers hypothesized that an H₂O ash on SiOCH film contributes to oxidation of the metal barrier, leading to poor copper adhesion.

A switch was made to an O₂ ash, and OES was used to correlate oxygen radical density with external ashing parameters, namely partial pressure and O₂ dissociation. Dissociation degree depends on pressure and power. For instance, at <1 Pa, the damaged SiOCH layer was <10 nm thick, though the ash rate was significant (500 nm/ min). Then, thermal desorption spectroscopy was used to determine how much SiOCH was converted to SiO₂ (damaged low-k) by excessive oxygen radicals. Where SiOCH was severely damaged, the copper and Ta/TaN interface had a higher concentration of oxygen, as shown by electron energy loss spectroscopy.

Electromigration lifetime was extended by 5× (Fig. 2 ) with the modified O₂ ash and modified fluorocarbon etch. Clearly, low-k damage and the quality of the copper/barrier interfaces are central to the yield and reliability of 90 nm and future dual-damascene interconnects.

2. Cummulative failure distribution plot of electromigration for a 24-via chain structure.

For additional information on yield management, go to www.semiconductor.net/yield