Top Tech Challenges for 2005

International SEMATECH (ISMT) recently released a list of the Top Technical Challenges for 2005, re-emphasizing advanced gate stack, 193 nm immersion and EUV lithography, and low-k dielectrics, and placing 3-D interconnect on the list for the first time.
 
ISMT uses the Top Technical Challenges list to focus resources on the most critical of ~90 projects that it maintains in semiconductor R&D. The ISMT research portfolio is developed by the consortium's Executive Steering Council (ESC), in consultation with corporate managers.

"This list of challenges reflects our members' view of where we can best utilize our key skills and resources for the benefit of both the SEMATECH membership and the industry," said Dr. Michael R. Polcari, ISMT president and CEO.

"Each of these challenges corresponds to critical infrastructure needs in lithography, advanced materials and manufacturing, as identified in the ITRS.

The top challenges reflect member consensus and include:

• Immersion Lithography — Optical lithography that interposes a liquid between an exposure tool's projection lens and wafer to achieve better depth of focus and resolution over conventional lithography. Recent industry symposia hosted by SEMATECH showed 193 nm immersion to be a viable technology for rapid introduction into manufacturing.
• Mask Infrastructure — Includes attention to improving the capabilities and reducing the overall cost of photomasks.
• Resist Strategy — A high-priority response to the requirements of new and emerging litho technologies, including 193 nm immersion and extreme ultraviolet (EUV). Line-edge roughness (LER) and limits of chemically amplified resists are among the strategy's focus.
• EUV Infrastructure — Includes the testing and development of masks, tool components, and resists to enable the introduction of EUV lithography into manufacturing later in the decade.

• Advanced Gate Stack — Involves the development of new gate stack materials and processes, primarily manufacturing readiness of hafnium-based, high-k dielectrics and metal gate electrodes.
• Non-Classical CMOS — An approach to the challenges posed by increased scaling of chip features. Challenges include infrastructure development (such as metrology techniques) for alternative device technologies, such as strained silicon, silicon-on-insulator (SOI) and double-gate metal-oxide semiconductor field-effect transistors.

1. SEMATECH’s 85 nm baseline is a critical enabler toward the development of a true, high-k/metal gate device.

• Low-k Dielectrics and Process Compatibility — Low-k is critical because it allows metal lines to be packed closer together on a chip with less risk of electrical signal leakage. ISMT engineers investigate low-k materials and assist layers necessary for successful integration and achievement of low k-effective values. The program includes extensive work in advanced barrier development, and understanding and finding solutions for ultrafine line copper resistivity increases seen at the 32 and 22 nm nodes.
• 3-D Interconnect Technology — Vertically interconnecting several chips to produce similar speed and density. In April, SEMATECH kicked off this effort by co-sponsoring a technical symposium and industry workshop in 3-D interconnect challenges and architecture.

• Metrology — A critical enabler to the achievement of increasing device densities and decreasing feature sizes on advanced semiconductors.

  2. SEM photo shows porous MSQ low-k material surrounding well formed copper lines connected by vias.

• Manufacturing Effectiveness and Productivity — Projects addressing equipment productivity, e-manufacturing, advanced equipment and process control, and standards development.
• Environment, Safety and Health — A cross-cut priority for each of the Top Challenges, addressing ESC considerations related to the introduction of new materials and process chemicals into advanced manufacturing.
• "These challenges demand innovative solutions," said Polcari. "SEMATECH is uniquely positioned to deliver to its members high-value, high-leverage programs in each of these areas, and to help lead the industry in realizing the Roadmap."

For additional information on wafer processing, go to www.semiconductor.net/wafer