"Pipe" Provides Express Lane for High-Speed Chip-to-Chip Signals

For an increasing number of applications, connection speed between die is an important factor in the decision between system-on-a-chip (SoC) and system-in-package (SiP) implementation. Silicon Pipe's (San Jose) off-the-top (OTT) packaging technology enables gigabit per second chip-to-chip communication, which can shift some of these decisions in favor of SiP and enable new SiP possibilities.

In a standard case, a chip-to-chip signal experiences impedance changes and parasitic losses as it passes from chip to package and from package to board, in addition to experiencing dielectric loss as it travels through the board. The OTT concept sends high-speed signals off the top of one package on a uniform impedance-matched transmission line to the top of another package (Fig. 1 ). Slower signals and DC connections are less sensitive to the impedance changes and dielectric loss, and they are routed through the package and circuit board. The transmission line can be a stripline or microstrip line, made using readily available materials and processes.

1. High-speed signals are sent between chips on a dedicated transmission line connecting the tops of the package substrates.

2. Contacts on top of the package substrate send high-speed signals to transmission lines. (Source: Silicon Pipe)

The high-speed signal connections from the die are formed on the top of the package substrate, and routed to the edges of the package (Fig. 2 ). The package is then encapsulated in a way that leaves the transmission line contacts exposed. The connections are readily accessible for probing.

The company has demonstrated data transmission rates over 20 Gb/sec for distances up to three inches using these OTT transmission lines running in differential current mode. With this capability, chips running at gigahertz clock rates could communicate with each other at full speed.

One of the reasons for choosing an SoC implementation over an SiP is the need for high data communication between many circuit blocks. With the ability to send signals between chips at the rates that OTT has demonstrated, this trade-off tilts more in favor of SiP. This would be most prominent in cases where the SoC die would be very large. Die yields tend to drop dramatically, and therefore cost rises dramatically, when the die size gets larger than 15 mm × 15 mm.

Another benefit of OTT is that high-speed data communication can be done without having to use serializer/deserializer (SERDES) circuitry. For many ASICs, including SERDES circuitry adds comparatively little to the cost of the chip, and it is quite common. For less expensive standard chips, it is very costly to add SERDES capability, comparatively speaking. The promise of connecting standard die together as though they were one die, inexpensively, presents some exciting possibilities.

There has been discussion over the years about inexpensive field programmable gate arrays (FPGAs) eventually competing against application specific ICs (ASICs). ASICs are much more expensive than FPGAs, but they provide much more performance. Connecting several FPGAs together with OTT technology might provide a module that competes with ASICs in terms of performance, and beats them in terms of price.

It remains to be seen what kinds of benefits OTT will deliver, but it promises great system performance gains with little additional cost. If it delivers, it will be a case of an interconnection-imposed limit being removed using packaging technology. Things like this must happen if Moore's law is to continue holding true.

For additional information on semiconductor packaging, go to www.semiconductor.net/packaging