One on One: A Closer Look at Nanoimprinting

Nobody can deny that semiconductor lithography continues to become a more and more complex beast. The days when people thought you couldn't print features at dimensions smaller than the wavelength of the light being used to do the printing are just a memory. Today's leading-edge lithography tools are using 193 nm excimer lasers to produce commercial chips at the 90 nm technology node. And 193 nm tools are expected to carry on into the 65 nm node and — with the help of a little water — even into 45 nm. And who knows? If the planets are all perfectly aligned and engineers can work out just the right flavoring in that water, maybe 32 nm is within reach of today's star wavelength as well.
 
It all sounds like a fairy tale come true. But it's not without a price. The complexity that lithographers, lens manufacturers, maskmakers, and anyone else involved in the lithographic process are faced with is phenomenal. It's a great balancing act, with trade-offs to be made around every corner. In addition to a plethora of resolution enhancement techniques (RETs), more recent discussions have even included the possibility of shifting from a 4× reduction ratio (the amount the pattern on the mask is optically reduced to achieve the size goal on the wafer) to a larger reduction ratio — perhaps 8×. There's surely not a chipmaker out there that actually wants to make this kind of shift — they would take a considerable hit in throughput — but they may eventually have to come to terms with the necessity of this kind of move nonetheless.

But life certainly doesn't get any easier in the next generation, despite a shift to a wavelength that would go back to being smaller than the feature size being printed. Extreme ultraviolet (EUV) lithography — the 13 nm frontrunner in the next-generation lithography (NGL) race that is scheduled to make its mainstream debut at the 32 nm node in 2013 — is anything but simple. Despite Intel's insistence on making it work (in fact, the chipmaker's roadmap marks its incorporation into production by 2009), EUV development is rife with obstacles, particularly with regard to sources and masks. Some question whether it will ever be ready for prime time. And if it does manage it, it'll come at a huge cost-of-ownership premium.

E-beam lithography — whether direct-write or projection — is another NGL candidate to hit the Most Likely list in recent years. But its throughput problems put it firmly in a toolbox reserved for such critical layers as contacts or vias, where it can really be of use.

Not surprisingly, then, the semiconductor industry has begun to take notice of a technique that harkens back to the 19th century, and wipes the slate clean of RETs, complex lightsources and reduction optics. Nanoimprint lithography (NIL) instead uses a 1:1 template to produce linewidths that have already gone beyond the 10 nm mark, and foresee virtually no limit in resolution. All of this at a price tag significantly lower than even today's leading-edge optical tools, not to mention the exponentially more expensive EUV alternative.

After almost a decade of work and investigation into the technology by several academic and industry groups, nanoimprint lithography finally made it onto the International Technology Roadmap for Semiconductors late last year, added to the list of possible candidates for post-optical lithography techniques at the 32 nm node.

NIL has been gaining attention and momentum, with more commercial manufacturers and investors joining the game. It is beginning to work its way from academia to commercial industry, although the industrial involvement is still primarily at the R&D level. Some of the biggest players in nanoimprint lithography grew out of university programs — for example, Molecular Imprints Inc. (MII, Austin, Texas) licensed its technology from work done at the University of Texas, while Nanonex Corp. (Monmouth Junction, N.J.) sprang from research at Princeton University. Stephen Chou, who founded Nanonex in early 2000 and is still a professor of engineering at Princeton, is considered a pioneer in NIL. Other major players in the field include EV Group (Schärding, Austria), SUSS MicroTec (Garching, Germany) and Obducat (Malmö, Sweden).

1. A transparent template is used as the “mold”in the room-temperature, UV-curable Step and Flash Imprint Lithography (S-FIL) process. The UV-curable technique is one of three broad categories of nanoimprint lithography methods. (Source: Molecular Imprints)

The hot embossing process uses a polymer that can be thermally modified to achieve patterning. The coating is heated above its glass transition temperature (T_g) to flow through the stamp, then is cooled again to set the design. Although "hot" may send lithographers running, fearing for their device thermal budgets (EV Group, for one, is considering a name change for its hot embossing technique) the relatively low temperatures applied are not considered to be an issue.

UV-NIL works in much the same way, except the coating is a low-viscosity monomer that is later polymerized by a halogen lamp, whose UV light crosslinks the resist layer to form a solid structure. SUSS MicroTec actually has a tool (the NPS200) that has both UV and thermal curing processes on one platform.

2. Shown here are the three nanoimprint techniques. UV-NIL (left) uses UV curing to polymerize a low-viscosity monomer; hot embossing (middle) thermally modifies a thin polymer film; and micro contact printing (right) uses a soft stamp in an additive technique. (Source: EV Group)

A third technique, commonly referred to as micro contact printing (µCP), is an additive technology. It applies a fluid directly onto a soft stamp, then the self-assembling monolayers attach to the surface to create a structure that requires no additional curing or temperature changes.

Besides these three categories of NIL, there are variations in terms of using step-and-repeat tools (much like today's optical steppers) or applying full-wafer techniques. Full-wafer or full-field techniques — as the names imply — print an entire wafer at once. Wafer sizes in this case are limited for a couple of reasons. One is that it is a difficult task to print large stamps. "It is very hard and time-consuming to print an 8 inch stamp with 10 nm features," said Paul Lindner, vice president and CTO of EV Group. Such an endeavor can take many months to complete, added Helge Luesebrink, EV Group's director of advanced lithography.

The other reason is the limited availability of large-diameter stamps. SUSS MicroTec, for example, offers just 4 inch capability on its full-field tools, according to Jörg Kühnholz, market development manager of nanopatterning for SUSS MicroTec. "This is not due to tool limitation (it typically goes up to 200 mm), rather the availability of a large size stamp," he said. "There is a rather high stamp cost due to the size, but this really depends on the feature size on the stamp itself." He also said that total thickness variation across the entire surface after imprint can be an issue, and thermal expansion can be an issue with full-field techniques.

On the other hand, full-wafer imprinting is faster than step-and-repeat methods, the equipment has a lower entry price, and it's easy to use for thick-layer applications such as MOEMS and microfluidics, Kühnholz said. In general, it has a good possibility of use for any single-layer applications. In some cases, the choice of full-field techniques may be a necessity. "Some applications can't use the step-and-repeat method," Lindner noted, because of stitching issues. Optical gratings, for example, allow no room for stitching errors, he added.

For mainstream semiconductor manufacturing, however, step-and-repeat methods will certainly be the way to go. It is a technology that mimics today's optical lithography techniques, so lithographers are likely to be more comfortable with it. More importantly, it is more compatible with silicon production — it can produce larger wafers without facing issues of stamp quality and cost, it lends itself better to alignment (which is not such an issue with other applications, but is paramount for semiconductor fabricaton), and it is not encumbered with thermal expansion problems.

Likewise, whether a manufacturer chooses hot embossing, UV-NIL or stamping also depends on the application. Promising candidates for the use of nanoimprint lithography are within the biomedical field — for microfluidics or biochips, for example. In this case, µCP may make the most sense because the UV light or heat of the other two methods could damage bio materials. On the other hand, µCP cannot produce the small features that the other methods can because it uses a soft, flexible stamp rather than a hard mold.

Hot embossing may be better suited to optical or MEMS applications rather than semiconductor applications for several reasons. For one, hot embossing requires that the temperature be uniform across the substrate surface, which makes it more compatible with full-field templates (and thus less compatible with silicon). Also, because of the high viscosity of the polymer layer in hot embossing, it requires a fair amount of pressure (typically ~107 Pa) to get the polymer to flow evenly through the structures, which can cause deformation of the wafer. Because of the required heating and cooling cycles involved with hot embossing, imprinting an entire 200 or 300 mm wafer is time-consuming. For this reason, though, developers are researching polymer materials with a low T_g, Kuenholz noted. "Currently, there are already materials with a T_g of 60°C and lower."

UV-NIL, with its step-and-repeat functionality, looks to be the likely candidate for semiconductor manufacturing at the 32 nm node and beyond. Its low-viscosity monomer is better able to flow through the complex designs and small features of semiconductor chips, and requires only a small amount of pressure to minimize wafer deformation. This method does not create the final pattern directly from the template onto the wafer, but rather imprints the pattern onto a transfer layer, which is then etched onto the wafer, much like with photolithography. This means that the aspect ratios of the transfer layer do not have to be very big — as small as 2:1 — thereby minimizing the thickness of the resist film. Through etch, aspect ratios can then be made at up to 10:1, according to MII.

Most toolmakers apply the low-viscosity layers of UV-NIL through spin-coating. But spin-coating an entire wafer at once creates a uniform layer that cannot effectively fill complex designs with varying pattern density, according to S.V. Sreenivasan, founder and CTO of MII. To enable simultaneous imprinting of both dense and sparse features during the same imprint step, MII dispenses varying-size droplets of its monomer immediately prior to each imprint and cure step (Fig. 3 ).

3. Rather than spin-coat the monomer uniformly across a wafer, the S-FIL process dispenses monomer in tiny droplets to compensate for varying pattern density. (Source: Molecular Imprints)

Nanonex's Chou argues, however, that MII's method of monomer dispense is time-consuming (he compares MII's process time of 60 sec/die with Nanonex's time of 5 sec/die), and makes no difference in liquid flow through the template. "The droplets that MII uses are several hundred microns, but the density variance is 10-50 µm. So the variance is much smaller than the size of a drop," he said. "With spin-on, when you press the template down, the liquid flows inside the die easily."

Regardless of the monomer dispense method, UV-NIL also offers improved alignment over other techniques. The use of a transparent fused silica template allows not only UV curing through it, but also optical alignment. Alignment in nanoimprint is helped by the fact that there is <250 nm of space between the template and the wafer — rather than inches of space between the mask and substrate in optical lithography. But the mask aligners and substrate bonders of other NIL methods do not offer active alignment; precise alignment is not required in many other MEMS or optical applications. "Alignment is the one piece that the other guys don't need, that silicon does," Sreenivasan said.

Although UV-NIL does offer active alignment, capabilities vary substantially from manufacturer to manufacturer. For example, EV Group has achieved an overlay of 50 nm, with a target of 10-20 nm. SUSS MicroTec is at 250 nm, but expects to be offering something more like 20 nm within the next three years. Meanwhile, MII is making use of its low-viscosity (<5 cP) monomer to achieve what it calls in-liquid alignment. Alignment can be fine-tuned in situ, after the template is pressed into the liquid. "Viscous liquids won't let you move around like that, and polymers are highly viscous," Sreenivasan said. "We use very low-molecular-weight monomers. We take advantage of the liquid state, and can achieve ±6 nm alignment."

Another improvement task on hand is throughput, although toolmakers say they haven't spent much time yet on trying to improve it. MII, for example, expects a throughput of 5 wph by the end of this year, with 25 wph by the end of next year, according to Sreenivasan. "It's not really that much of a concern. Our customers are more focused on the process quality," he said. "The tool cost is so low, throughput has not been a priority so far."

Of greater concern is defect density. "The first thing to overcome is defect density," Chou said, noting that alignment is good enough for some applications. "But people are just starting to categorize defect density and where it comes from."

4. Although photolithography lines can typically be made smaller through etch or other shrinking techniques, pitch is harder to fudge. Shown on the far left are 5 nm lines printed through NIL, with a 12 nm pitch. (Source: Nanonex)

Even better, nanoimprint offers the opportunity for 3-D capabilities in a single imprint. "One big advantage of imprinting in general over standard litho or steppers is the fact that one can create several functional layers within a single imprint," Kühnholz said. "That will for sure open new doors for IC manufacturing."

Since NIL was put on the ITRS last December, the NIL toolmakers have certainly been getting more questions from semiconductor manufacturers. But whether nanoimprint ultimately has what it takes to beat out such contenders as EUV lithography or 193 nm immersion lithography at the 32 nm node, toolmakers are content that there are plenty of other markets for them to pursue.

5. Nanoimprint lithography shows promise for multilayer processes. In this example, the imprint process and final SEM is shown of 60 nm channel MOSFETs on a 4 in. wafer. (Source: Nanonex)

"We don't want to limit ourselves to this one application, because the possibilities are much broader," noted Peter Podesser, President and CEO of EV Group. There are still a lot of technical feasibility studies that need to be done before NIL comes close to market adoption at volume production levels, he added.

Whether imprint lithography will actually make it into high-volume semiconductor production is still questionable, according to Kühnholz. "Because, in the same time imprinting is developed, the classic UV stepper will not stop to develop their process to lower resolution," he said, pointing in particular to immersion lithography. "I personally think that, before one will swap from a well known process to a rather risky process, a lot of cost saving needs to be proven."

Podesser is somewhat concerned, actually, about all the attention ITRS placement has brought to nanoimprint lithography — even more so the attention that nanotechnology has been getting. "Nanotechnology is very fashionable, which can pose a danger also," he said. "There's a very inflationary use of the word 'nano'— I hope there's not a negative impact on development. It could get oversold." He saw a similar occurrence with optoMEMS devices, whose bubble exploded in 2001, leaving collateral damage.

"We take it seriously that the ITRS has included NIL. But we are cautious as well, since SUSS has seen many things come and go over its 55 years of serving the semiconductor industry," Kühnholz said. "I guess the next five to 10 years will show if NIL will find its way out of the lab into real production, especially for IC fabrication."