Hans Stork, Texas Instruments Senior Vice President and CTO

Hans Stork (Source: Texas Instruments)

Hans Stork is senior vice president of silicon technology development and CTO of Texas Instruments (Dallas). Stork joined TI in 2001 from Hewlett-Packard, where he served as director of the Internet Systems and Storage Lab at HP Laboratories, and earlier as the director of the ULSI Research Lab. He began his professional career at IBM, where he researched advanced bipolar technology and circuits, and later SiGe technology, finally assuming responsibility for the Exploratory Device and Technology programs at IBM Research. He was elected IEEE Fellow in 1994 for his contributions to SiGe devices and technology, and is a fellow member of the IEEE Electron Devices Society. He joined the International SEMATECH board of directors in 2002, has been a board member of the Semiconductor Research Corp. since 1999 and serves on the Semiconductor Industry Association's Technology Strategy Committee. Additionally, he has been a technical advisor to government efforts on high-performance computing benchmarks and national security issues emerging from Internet computing. Stork received the Ingenieur degree in electrical engineering from Delft University of Technology, and has a doctorate from Stanford University.

SI: Do you expect to change anything in TI's technology roadmap?

Stork: No, I am very much on board with CEO Rich Templeton's direction, which is to continue leveraging leading-edge technology for communication-centric products — the space where DSP and analog excel. Things may change in four or five years; however, right now there don't seem to be any compelling reasons to change. We believe that our involvement with communication-centric DSP and analog products could have a very long run — it's a market segment that grows faster than the industry average.

SI: What are your thoughts on the ITRS?

Stork: It's a guideline that represents a consensus. Because of this, some consider it somewhat conservative. I could also point to instances where it's been overly aggressive, such as the expected progression of low-k materials, for example. As a general guideline, it does a good job in identifying issues at stake. As to its being exact in terms of timing, this is something that, overwhelmingly, is determined by the marketplace's response to a fluid combination of technology, fashionable features, cost and availability. In a market that's so fast moving and competitive, a one-year granularity is too rough a guideline when being three months early or late on something can be tremendously significant. In terms of planning and instituting technology investments, one certainly must exceed the one-year range and cyclicalities.

SI: Wireless voice and multimedia devices seem to be some of the industry's major technologies and drivers. What is your perspective on this?

Stork: One of the more compelling things we can enable is more seamless wireless communication across a multitude of platforms and protocols. The hardware can enable the selection of the correct kind of radio, while protocols — depending on the environment — adjust data rates and transfer capabilities in a user-transparent way. This would open a still wider range of applications, making the use of these communication capabilities far more pervasive in cell phones, PDAs and many other products.

SI: Analog integration in CMOS is a major focus area for TI. What's going on right now, particularly with your copper and system-on-a-chip work?

Stork: We believe that, for these high-volume market segments, single-chip integration provides a cost-effective product implementation. We've searched for ways to make the analog interface more flexible and provide RF capability on the same die. Our ideal might be described as making RF and analog functions into just another ASIC cell in the library — something that can be implemented when needed and scaled into the next generation just as we do with digital blocks today. This not only provides a very cost-effective implementation, but also is a strong competitive advantage because what used to be various individual chips are no longer accessible to other suppliers. This will help us strengthen our market position. This kind of advancement requires leading-edge technology, so that on a die-size level you can get the most efficient implementation. On the design side, the tools and expertise are the test and verification that allow you to deal with these complex systems.

SI: What is the status of your 65 nm work?

Stork: At the VLSI Symposium in Honolulu, Hawaii, we presented some of the impressive progress we're making on controlling leakage current and increasing mobility using localized strain techniques, so we believe we're tracking close to the desired progress curve. Our goal is to qualify the first product at the end of 2005, with first samples available earlier in the year. Conceptually, everything seems straightforward. (Laughing) There are always some devils in the details! However, there are no more choices left to be made in terms of what we need to do.

SI: TI recently became a core member of IMEC's sub-45 nm CMOS research program. What is your perspective for that technology node?

Stork: We're involved in the 45 nm program, and are devoting increasingly more resources to it. For us, it takes a good two to three years to mature the technology development. There are still many options on the table in terms of technology choices, which haven't been ironed out yet — many more choices than we had to make for 65 nm.

SI: For example?

Stork: Lithography, for one. To meet our design rule objectives, we need immersion 193 nm lithography. While it looks very promising, it's far from proven — there's a fair amount of risk. Second, to meet the high-performance flavors of that technology, we'd need a metal gate and/or high-k gate dielectric in the transistor structure — also far from being proven. Thirdly, we've always been conservative and believe we should continue being so on the interconnect level. Getting an effective <2.5 low-k will be extremely difficult within that time frame unless there is some unexpected breakthrough. When you factor these together, you're facing a pretty enormous challenge. I believe that 45 nm will be a difficult transition.

SI: New materials and processes are being introduced at a rate that would have seemed impossible as little as five years ago. How do you view the challenge?

Stork: My gut feeling is that we haven't improved our ability to introduce more than one new material or process per node, per generation. An important focus of our strategy is making choices in the correct sequence. Taking one step at the wrong time can push you back two steps. To stay at the leading edge while implementing a new material on a new generation, while making improvements on everything else, stretches the ability of what a given team can do. We must trade off the various choices we have, with the logistics of keeping things down to one variable at a time. Of course, one can be very clever as to what that means exactly — take smaller steps in between to implement something before bringing it to volume production. Even so, simultaneously introducing two variables remains very risky.

SI: Increasingly, packaging is becoming a part of the circuit itself. How do you see the technology evolving over the next couple of years?

Stork: I expect the diversification that we've experienced over the last two years to continue for a while longer. Then I think it'll be followed by some sort of a shakedown. The phase we're currently undergoing is one of recognizing that packaging is another technology we must optimize to obtain the greatest possible benefit from the silicon system. Over the last couple of years, the industry has come up with a number of ideas on how to do this; however, I don't believe that the market will bring all of these to full fruition — some will have a short life.

SI: Which will survive?

Stork: The SiP, or the stacked die, stacked package will rapidly gain acceptance for a number of market segments. At the same time, we expect that flip-chip and ball grid arrays will gain market share. This will be a reflection of not just continued performance growth, but also of continued improvements in cost reduction. The drive towards environmentally friendly materials will make all of these more challenging, particularly because lead-free materials are more brittle and difficult to work with. Packaging is becoming a more critical link in the device performance chain. As such, the electrical design and its interaction on the board is quickly gaining in importance.

SI: What do you view as the biggest challenge that the device designer/maker faces over the next four years?

Stork: The gate stack — the combination of dielectric, gate material and channel profile — and the engineering around it, including desired strain to maximize mobility is the key bottom parameter. We're running into SiO₂ and modified SiO₂'s physical limits. We modified it with nitrogen, and now we must go a step beyond that and use metallic compounds to attain the desired electrical properties. The gate material must also become more metallic for different reasons, such as getting a minimum amount of depletion. Integrating all this while shrinking dimensions is something that the industry hasn't done since the 1970s. We've been using polysilicon and SiO₂ for most of the industry's development, so this will be a huge change. At the interconnect level, we're reaching genuine physical and electromagnetic limits. We know of no better workable conducting material than copper. Silver is marginally better, but its melting temperature makes it incompatible. Progress in low-k materials will be made difficult by the need to maintain chemical and mechanical stability, integration robustness, and so forth. It's now up to the design community, more than ever, to maintain performance.

SI: Is the design software up to the job?

Stork: There is no doubt that it was our design capabilities that made possible the current levels of integration in silicon. If it hadn't been for the simplicity of MOS devices and the possibility to automate to do complex things, our ability to do shrinks would have been affected. One of the challenges design software now faces is the sophistication level it'll have to provide where transistor parameters shift as a function of time, where they must include performance at the transistor level, at the interconnect level, where they must deal with power dissipation as well as speed performance and all the various trade-offs therein. Design tools' complexity has risen exponentially — just to keep them good enough to enable us to continue doing what we're doing would satisfy most of us. People have asked us why are we not building in 3-D. A main reason for it is that the tool capability runs too short to enable us to grasp things in 3-D. It is more than an order of magnitude more difficult to do such a design, and we lack the visualization, automation, capture capability to do 3-D — we have a hard enough time with 2-D.

SI: What do you see as the impact of offshoring on device design in particular and on the industry in general?

Stork: With manufacturing's center of gravity shifting that far away, it may seem difficult to expect that the U.S. will maintain the development and problem-solving excellence that has characterized it until now. Too much offshoring could have a serious effect on the country's engineering profession and on its capability to retain and grow a technology infrastructure. A balance is possible, but the rate at which things have been moving away lately is certainly a cause for concern.

SI: Most offshoring is going to Asia, particularly China. Do you have any concerns about the IP situation there?

Stork: China is well known for its different attitude toward IP, different to that of the West. Such a significant cultural clash becomes a major issue, particularly since it's very likely that they will be able to provide the same leading-edge technology as we have in the Western world — that's merely a function of time. I am not saying that this is good or bad; merely that it will create an economic balance quite different to the one we're used to.

SI: Are there any industry trends that we ought to give more attention to?

Stork: The industry's cost structure. There are many aspects to this, but the thing to really pay attention to is the cost of our processing equipment. The need to pay $30 million for an advanced scanner system prevents us from doing off-the-beaten-path, exploratory ideas. Having to keep the equipment in production at all times to get the ROI dampens creativity. We must encourage the work of academia, research labs and startups to determine whether it is possible to do similar work at an order of magnitude less cost. This could have more of a payoff on our industry than going the other way.