No Significant Materials Changes for 65 nm?

Asked to sum up the technology and business challenges in the transition from 90 to 65 nm, panelists at a DuPont event during SEMICON West came up with some interesting conclusions:

• High-k gate dielectrics will not be used at the 65 nm node, but will wait until 45 nm.
• 65 nm technology will be on time.
• 65 nm appears to be the 300 mm generation, but the jury is still out on 65 nm/200 mm wafers.
• 90 nm low-k materials (k~2.8) will be used at 65 nm.
• Fewer new materials will be introduced at 65 nm than originally anticipated.
• A new business model for new materials creation may be needed to enable ROI and company sustainability.

Dr. Mehdi Moussavi, equipment supplier manager for the Silicon Technology Platform at LETI (Grenoble, France), said the industry will not be introducing radically new materials at the 65 nm node. "There is no mature enough high-k gate stack today that makes people comfortable enough to implement it in production." Elaborating on the point, he said that, while high-k dielectric development work is very advanced and stable materials have been identified, the problem lies in selecting stable n+ and p+ metal gates.

John Caffall, director of operations at the submicron development center of Spansion (Austin, Texas) agreed, pointing more to evolutionary changes rather than revolutionary at 65 nm, such as more selective slurry for CMP. "Since the focus of Spansion is flash memory products, from a materials standpoint, we are not challenged in low-k as we are in advanced logic devices, though we'll eventually be looking for a breakthrough in the 2.5 k level or less. We're seeing a plethora of next-generation substrates, such as SOI and strained silicon, and in flash we use a low-COP material, and beyond new materials, lithography is always a great challenge — making phase-shift masks successfully in the masks shops and making them cost-effectively."

Bill Rozich, director of 300 mm semiconductor operations at IBM (East Fishkill, N.Y.), talked about whether the 65 nm devices will be fabricated on 300 mm only. "We think it is the 300 mm generation, but when you look at the tightness of the specifications, which is driving tool matching and tool dedication at the gate level, this makes it very difficult for manufacturing."

Ken Monnig of International SEMATECH, the summit's moderator, questioned whether the 65 nm node marks the end of traditional scaling. Rozich responded that the emphasis has been on lithography excellence, and now materials integration has become just as important. "You can still go down the technology curve, but the techniques you have to apply to stay on the curve have changed." Caffall said, "Integration presents the greatest challenges at 65 nm, and trying to work materials integration with a design-for-manufacturing strategy is going to be imperative as we move forward." LaMar Hill, director of business development at Albany Nanotech (Albany, N.Y.) added that it is becoming very difficult to engineer the interfaces between materials, and getting repeatable interfaces is a challenge.

Mark McClear, global business director of advanced dielectric materials at Dow Chemical Co. (Midland, Mich.), explained that the industry's change from a small set of basic device materials to the invention of all new molecules requires a significantly different method of operating and drives the need for new business models. "It's a long runway, from new material creation, getting a compatible toolset, integrating the material to producing reliable devices, and the challenge is motivating a materials supplier to dedicate that time and R&D dollars to a material that may take over a decade to begin producing revenues." McClear noted Intel Capital's recent investment in a materials supplier, TriChem. "That's the kind of thing that can prime a pump and help a materials company get over this 10-year horizon and make an impact downstream."

Moussavi agreed that there is a need for more collaboration among materials suppliers, R&D centers, and device manufacturers at an early stage of work, so that test wafers and real device evaluations can be expedited. He said that the advantage of the ST/Philips/Freescale alliance being literally next door to LETI allows short loop runs on test wafers and an early look at reliability.

Caffall noted that AMD and IBM decided to follow a new business model with their collaboration on 65 nm technology development on 300 mm. "The type of partnership a company selects depends on time-to-market, effectiveness of development, effectiveness of the portfolio, its other various partnerships, and generally, a company measures from its bottom line and the success of its technology and products."

With respect to whether 65 nm products will be delivered on time, Rozich and Caffall said their companies are on schedule and expect to deliver as planned. Moussavi agreed, "I'm much more worried about 45 nm, because then you really need to introduce a lot of new materials. However, even for 45 nm, there's always a plan B."