The Lead-Free Challenge: Materials for Assembly and Packaging

Get the lead out. That was the message emanating from Japan in the late '90s and is now echoed by the European Union (EU) through strict legislation. While the toxic impacts of lead are well known, it is still hotly debated whether lead from electronics really is a threat to humans or the environment. There is concern about the leaching of lead from discarded electronic devices in landfills, as well as lead mining and processing. Toxic emissions during the recycling of lead-containing devices^1,2 is also a concern. Most of the alternatives under discussion do not pose a threat with regard to toxicity, but could have other environmental impacts. For example, elevated melting points mean more energy consumption. On the other hand, advanced equipment and new reflow profiles might, in certain cases, result in less power consumption at higher melting temperatures.³ An ecological drawback of silver-containing SnPb replacements is the immense energy needed to mine and process noble metal-containing ores.

After years of negotiations and half a dozen proposals, 25 EU member states are now implementing legislation that bans lead in electronics. By July 1, 2006, nearly all electronics produced for the European market must be free of lead. This includes information and communication technology equipment, consumer electronics, household appliances, tools (if not "stationary"), lighting devices and others.

Lead in solders for servers, storage and storage array systems and specific network infrastructure equipment is exempt from this regulation until 2010. Also, solders with more than 85% lead are exempt. By order of the European Commission, a study is underway to evaluate further exemptions, including flip-chip-in-package interconnections used in today's high-performance PC processors. Many of these are mounted to their carrier substrate using high lead-containing C4 (controlled collapse chip connection) balls. The EU directive on restriction of certain hazardous substances, such as lead, allows exemptions from the lead ban in cases where replacement is "technically impracticable," but information on the alternative soldering processes needed for these kind of devices is not readily available. Also, the scope of the directive is not defined as exactly as needed. For example, consumer electronics are covered by the lead ban, but automotive electronics are not, so what about car radios? In this case, it was clarified that car radios are exempted from the lead ban, but several other cases are still awaiting final guidance.

The lead-free legislation in the EU will affect the electronics industry worldwide, partly because of the worldwide supply chains, but also because this legislation is an archetype for similar legislation in other countries. For example, China proposed similar legislation banning the same substances and also set a July 1, 2006, deadline.

Now, on the road to being free of lead, extensive materials research and process qualification are required for flip-chip and wafer-level packaging, SMT and wave soldering. We have been investigating suitable materials and processes for flip-chip-on-board and chip-scale package technology.

The bumping process (Fig. 1 ) requires an under-bump metallization (UBM) to be clad with the new solder material. The printing process is followed by reflow at a temperature ~20°C above the melting temperature of the solder, which is then followed by cleaning and final bump inspection.

1. The bumping process requires an under-bump metallization to be clad with the new solder material.

UBM needs to be compatible with new solder materials and is performed by an electroless nickel process. The wafers are treated in a sequence of chemical baths. Pad cleaning is followed by zincating to activate the surface, deposition of nickel (5 µm), and an immersion gold layer. The process has been developed by Fraunhofer IZM in cooperation with the Technical University of Berlin. Electroless nickel UBM is a well established, high-yield process now being used worldwide.

Solder printing requires fine-pitch stencils, solder pastes adapted for fine-pitch applications and optimized printing parameters. Several lead-free solders have been made available by solder paste suppliers, including SnAg_3.5, SnAgBi_xx and SnCu_0.9. One of the leading candidates for eutectic lead-tin solder replacement, Sn_95.5Ag₄Cu_0.5, was successfully tested at comparable process yields to SnPb solder. Squeegee speed and requirements for stencil wiping and inspection determine the throughput. With a typical stencil thickness of 80 µm, bumps with a height of ~110 µm are achieved.

The difference in melting temperature, increasing from 183 to 217°C for the SnAgCu_0.5, is reflected in the thermal profile of the reflow oven being increased from ~205 to 235°C. Typically, the reflow atmosphere is nitrogen to ensure a minimum reoxidation.

Also, to ensure a high process control, the bumped wafers have to be inspected by automated optical inspection. Instead of 100% inspection, recent research indicates that dedicated test structures for bumping may suffice to ensure a high bump quality, minimizing inspection times. Because the optical inspection of SnAgCu bumps is influenced by the rougher appearance (compared with the shiny surface of the previously used SnPb solder), this step is more critical and needs closer attention.

Despite some issues identified so far, cost calculations have indicated that replacing SnPb for FCOB applications with SnAgCu0_0.5 may result in bumping process costs well below $50/wafer for high-volume production.⁴

Although the technological descriptions so far highlight aspects for flip-chip bumping, with the advent of fine-pitch chip-scale packages (>0.5 mm pitch), the solder deposition method using stencil printing becomes a viable alternative to the current workhorse of solid sphere placement.

The worldwide trend toward lead-free electronics, as well as the demand for high melting solders for the automotive sector, has pushed the industry to alternative solder systems. One concern regarding these new systems is their reliability. Because of slightly higher yield stress and slightly lower fatigue ductility of SnAgCu compared with SnPb₃₇, fatigue life and failure mechanisms are assumed to be nearly identical for both solder alloys.⁵ In practice, the thermal history and geometry of solder joints play a dominant role in the fatigue life, not the alloy composition.⁶ For electroless nickel UBM, Popelar et al.⁷ demonstrated an excellent shear performance for SnPb₃₇, as well as for Sn_95.5Ag_3.8Cu_0.7 solder bumps. In addition, underfilling — typically needed for reliable performance of any flip-chip product on laminate PCB — will remove much of the stress from the solder joint, thereby extending lifetime to the desired range.

Two reflows — one reflow process for ball formation on the wafer and one reflow process for assembly — are typically used in flip-chip processing. Ni₃ Sn₄ is the intermetallic compound that forms for SnPb as well as for SnAgCu solders on an electroless nickel UBM.⁸ For Sn_95.5Ag_3.8 Cu_0.7, the morphology of the intermetallic after two reflows is described as regular and chunky. Solid-stage aging is especially relevant for flip-chip applications at elevated temperatures; aging for 1000 hours at 150 and 170°C shows a consumption of nickel transforming into Ni₃Sn₄ of <2 µm for SnPb, as well as lead-free alloys. The thickness of consumed nickel is approximately doubled for Sn_95.5Ag_3.8Cu_0.7, compared with eutectic SnPb.⁸ Aging at 170°C instead of 150°C means for Sn_95.5 Ag_3.8 Cu_0.7, as well as for SnPb, an increased thickness of consumed nickel by a factor of about four.

Shear tests of solder bumps after high-temperature storage at 150°C for a period of 2000 hours result in higher shear forces for Sn_95.5 Ag₄Cu_0.5 than for SnPb₃₇. Furthermore, shear test results for Sn_95.5Ag₄Cu_0.5 after temperature and humidity storage (85°C and 85% RH), as well as after thermal cycling (-40 to 150°C, 1000 cycles), are slightly better than for SnPb₃₇.⁹ Also, Wölflick and Feldmann¹⁰ tested flip-chip assemblies at cycles of -40 to 125°C, resulting in a much better long-term stability for Sn_95.5Ag_3.8Cu_0.7 compared with SnPb₃₇, whereas Schubert and Dudek¹¹ stated lower reliability for Sn_95.5Ag₄Cu_0.5 than for conventional SnPb₃₇ (cycles -55 to 125°C and -55 to 150°C). For both cases, the choice of underfill material, amount of flux residuals and actual joint height will determine which type of contact performs better. This indicates the choice of the alloy is only a second-tier factor for the reliability of the product.

Tin-rich solders are currently considered for applications in a 150°C environment. For even higher temperatures, eutectic gold-tin (Au₈₀Sn₂₀) solder or silver-filled adhesives offer a working range of temperatures up to 200°C.

Focusing on CSP contacts, where usually no underfill is employed, the greater mechanical resilience of the lead-free solders is expected to increase the lifetime of the device. However, care must be taken because the failure modes may shift from fatigue cracking to brittle cracking in the thicker intermetallic phase or even delamination of the metal pad from the carrier substrate, as the occurring stress is not relieved in the solder bump by creep of soft SnPb, but transferred to the interfaces via the resilient lead-free solder.

Solder pastes required for wafer bumping are type 6 (5-15 µm) pastes to ensure a homogeneous volume of printed solder and thus a decreased variability of bump heights after reflow.

Compared with conventional SMT solder paste printing on PCBs, the smaller particle size of ultrafine-pitch pastes means higher viscosity, which can significantly influence printability and paste release from the stencil. The enlarged surface-volume ration means an increased oxidizability of the solder alloy and thus a higher oxide content in the solder paste. Consequently, an adaptation of activators is required, and the reflow process needs a nitrogen atmosphere.

The same manufacturing technology is applicable for lead-free tertiary or quaternary fine-pitch solder pastes as for SnPb₃₇ solders. The properties of lead-free solders include a lower tendency for separation because of lower density differences of lead-free alloys and flux.

Stencil printing is presently limited to minimum pitches in the range of 150-200 µm. For increased interconnection densities with ultrafine pitches and a broader range of bump sizes, electroplating is preferred. The electroplating process at Fraunhofer IZM is applicable for pitches down to 40 µm (Fig. 2 ). The International Semiconductor Roadmap for Semiconductors (ITRS)¹² predicts a decrease of bump pitch for flip-chip technologies in general from 160 µm in 2002 to 90 µm in 2010 and 70 µm in 2016 for high-I/O and high-power chips.

2. Solder bumps realized by ultrafine-pitch stencil printing (150 µm pitch, left) and electroplating (50 µm pitch, right).

Bump height uniformity of the electroplating process is in the range of ±1 µm, which means a significantly better uniformity than achievable with stencil printing because of variations in stencil material thickness and accuracy of laser cutting, as well as minor solder paste residues that remain in stencil openings. Here, typical variations are in the range of ±7 µm.

Yield losses of electroplating are in the ppm range or even less, which is much better than achieved by stencil printing, depending on failure criteria definition such as bump height uniformity. Consequently, for high-value, large-size ICs, electroplating might be the "low cost" technology, as yield losses make stencil printing non-competitive for these chips.

The UBM for electroplating consists of Ti/W/Cu layers sputtered uniformly over the entire wafer surface followed by a lithography process to define the bump pads. An additional layer of copper is electroplated, which is consumed partly by the solder during the reflow process and thermal stress that forms intermetallic compounds. The solder metals are deposited electrochemically from solutions based on methane sulfonic acid. Because process time for the electroplating process depends on bump height — contrary to solder paste stencil printing — electroplating is limited to smaller bump heights. After stripping the plating mask, the Ti/W/Cu UBM is removed by an etching process. The deposited solder on the wafer is reflowed to form spherical bumps, followed by a cleaning step to remove organic residues.

3. Electroplated SnAg bump after reflow, with a bump diameter of 100 µm.

At Fraunhofer IZM, electroplating of several lead-free solders has been performed and investigated in depth.¹³ The preferred alternative for SnPb solder is SnAg_3.5 (Fig. 3 ), which has some specific characteristics to be considered. Silver is more easily deposited than tin because of the high standard electrode potential difference. Therefore, a very strong complexing agent is needed for silver ions to inhibit their preferential precipitation.

Whereas the Sn-Pb binary phase diagram shows that small deviations in solder composition do not influence the melting point significantly, the situation for Sn-Ag is much more critical. Even a small addition of silver to the eutectic composition of 3.5% silver induces a large increase in the melting point. Furthermore, investigations at Fraunhofer IZM showed for a silver content of 4% and higher the growth of large plate shape Ag₃Sn intermetallic compounds, which are a serious problem for interconnection reliability. For electroplating, the consequence is a very strict control of the bath and alloy composition for eutectic SnAg_3.5 plating. Ternary alloys are even more critical to process by plating and should not be considered. On the other hand, as the copper plating of the UBM dissolves partially in SnAg, the reflowed bump consists of SnAgCu alloy anyway and can be influenced by the reflow temperature.

The consumption of the copper-plating base is increased with SnAg compared with SnPb. Therefore, an appropriate thickness of electroplated copper has to be provided for. Concerning process costs, there is no significant difference between plating of SnPb and SnAg (Table ).

The examples of stencil printing and electroplating wafer bumping describe the current status of lead-free alternatives for advanced interconnection technology, showing that reliable lead-free technologies are available. Nevertheless, time is growing short to implement these processes in order to meet the 2006 deadline, and the supply of lead-free materials and components is still a critical issue.

The latest findings in material research for lead-free applications, as well as implementation and legislation issues, will be presented at Electronics Goes Green 2004+ in Berlin, Germany, Sept. 6-8, co-organized by the IEEE Components, Packaging and Manufacturing Technology Society. The conference program is available at www.egg2004.izm.fhg.de.