Low-Downforce Planarization Combines Electropolish and CMP

A new technology for planarizing copper with inherently low downforce, a prerequisite for copper/low-k structures, has been introduced on the Reflexion LK ECMP from Applied Materials (Santa Clara, Calif.). The ECMP technique, which combines aspects of electropolishing and conventional CMP, was presented in a joint paper with IBM at the International Interconnect Technology Conference in June and formally announced last month at SEMICON West. It is available on the company's 300 mm Reflexion LK platform (existing LK tools can be upgraded). The LK is a second-generation 300 mm CMP system introduced in 2003; the first Reflexion was introduced in 2001 as a successor to the company's Mirra 200 mm tool.

ECMP is planarization and process control by electric charge. The charge is applied in three different zones across the wafer to adjust for variations in topography (i.e., thicker or thinner edges and centers). Most importantly, this charge-based method provides planarization, which is unlike the isotropic removal of electropolishing. Another significant advantage of this combined CMP and electropolish approach is that 10× lower downforce can be used (about 0.3 psi), which is critical to minimize stress on low-k dielectric materials that are layered within copper devices.

Figure 1 shows how the pad is used in conjunction with an electrolyte solution instead of a slurry. Copper removal occurs where the pad contacts the topography, while there is a minimal amount removed where there is no contact. A passivation layer protects the unplanarized copper, which minimizes dishing.

1. A new planarization process with inherently low downforce combines aspects of electropolishing and conventional CMP. Note that an electrolyte is used instead of a slurry, and lower areas are protected by a passivation layer that minimizes dishing. (Source: Applied Materials)

"CMP today uses a balance between the mechanical and chemical components for abrasion and dissolution to achieve planarization," explained Robert Ewald, global product manager, ECMP, at Applied Materials. "With ECMP, we introduced an electrical component, so the reaction becomes more electrochemical and less dependent on the mechanical downforce. We take the planarization capability of CMP, the downforce independence and low cost of electropolishing, combine these together to form a new planarization solution, ECMP. We shift the operating regime to near no-shear force."

Ewald said the removal rate is independent of the downforce but controlled by the voltage applied (voltage directly controls the charge). "The removal rate now is voltage-controlled as opposed to downforce-related."

As shown in Figure 2 , the removal rate is controlled by the charge. "It's a linear relationship, so the greater the applied voltage, the higher the removal rate," said Ewald. The fact that this is a linear relationship is not only a function of the physics and chemistry, but of the design of the system. "The efficiency of the process cell creates close to 100% ionization, which means all the copper is accounted for. Since we can account for all the copper, we have a very predictable and repeatable process."

2. Copper removal is determined by the amount of electrical charge. Topography across the wafer is optimized by three zones of control.

The passivation process, which employs a layer of copper oxide (Fig. 1 ), suppresses removal in the recessed areas, said Ewald. The passivation layer has a much higher resistance than the exposed areas, allowing copper removal to be localized. "As we remove the passivation from the areas that contact the pad, we have electrical dissolution (removal) of the copper," he explained.

Another advantage of the approach is that it enables in situ realtime current-control endpoint detection. "We take advantage of the inherent current in the process for precise and predictable endpoint control," Ewald said. "Since we have a linear relationship between removal rate and charge, the charge can be used to determine exactly how much copper we want to remove from the surface of the wafer."

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