System-in-Package Uses Silicon Substrate

For as long as flip-chip technology has been around, silicon has been examined as a package substrate material, in part to avoid coefficient of thermal expansion (CTE) mismatch problems. In recent years, silicon package substrates have been used to increase interconnection density for system-in-package (SiP) applications. STATS (Singapore) recently announced the availability of its chip-scale module package (CSMP) for the integration of passives and ICs in an SiP module, using silicon as a substrate.

The company manufactures integrated passive devices (IPDs) on the silicon substrate using thin-film techniques. One or more die are flip-chip attached to the IPD substrate, which is then packaged as though it were a regular silicon die, using either flip-chip or wire-bond attachment (Figure ). The resulting SiP can be in the form of a ball grid array (BGA), land grid array (LGA) or quad leadless package (QLP).

The package is intended for applications that require highly precise, physically small passives, such as wireless and RF transceivers, front ends, and amplifier modules for mobile devices. It can also be useful for miniaturized analog circuitry, whose characteristics can be very sensitive to passive device characteristics.

The die containing integrated passive devices (IPDs) is connected to the silicon die and the package substrate in flip-chip and wire-bond configurations.

As a SiP module, it offers the standard SiP advantages. System components can be made on separate die, so they can be made with their optimal processes and on their optimal materials. For example, memory and logic can be made on separate die if it optimizes cost and performance. Silicon germanium can be used where desired for low-power and wireless chips, while other die can be made of silicon, GaAs or other materials.

One issue held against the use of silicon as a package substrate is that the silicon is utilized much less efficiently than when it is used for ICs. While it is true that the silicon used to make hundreds of passives in the CSMP could be used for millions of transistors instead, those passives are absolutely essential, and it is difficult to make them any cheaper.

The truth about the cost of using silicon as a package substrate is that the silicon itself costs comparatively little. If only a few mask steps are used to make the passives, this approach can be less expensive, and much simpler than placing multiple 0201 passives in a small package, for example.

One of the advantages of using silicon is that well established tools and processes are available. Silicon IPD substrates can be made very repeatably using readily available equipment. With 20 µm lines and spaces, most bumping facilities could perform most of the processing with their current equipment sets. The company claims component value tolerances within 3%, and within 1% for components of the same nominal value within any given module, without laser trimming.

The silicon itself helps with the predictability of component values and models. In high-Q designs, such as those used in wireless applications, the AC response of inductors and wiring traces varies significantly with the surface properties of the substrate. Silicon is readily available with an ultrasmooth surface. This not only minimizes the effect of the substrate's surface properties on component values, it also makes those effects very predictable.

Like any SiP substrate, an IPD substrate is essentially a small circuit board in a package, requiring careful design. The characterization of structures made in and on silicon is well established, so it is a straightforward matter to provide accurate models. The company offers an extensive library of models and design tools. In addition to the standard resistor, capacitor and inductor elements, the libraries contain baluns and Chebyshev filters, along with full electrical models for all elements.

In a way, CSMP is an example of something old becoming new again. Decades ago, diffused resistors were made on the IC itself in the production of resistor-transistor logic (RTL), until transistor-transistor logic (TTL) proved to be more efficient. In a time when TTL's successor, CMOS, may be running out of steam, the making of passives on silicon is coming back to enable handheld wireless devices that old RTL designers could only have dreamed of.

For additional information on semiconductor packaging, go to www.semiconductor.net/packaging