Copper Improvements Coming From Every Direction

At the annual International Interconnect Technology Conference (IITC), low-k dielectric developments typically steal the headlines. Or it's the novel air-gap approaches and system-level interconnect modeling that has the audience walking away inspired. Though this year had its share of those types of novelties, it was the more subtle modifications to the mainstream copper process that really stood out as the likely solutions for tomorrow's interconnect solutions.

One important example is the metal caps on interconnect lines, most commonly cobalt tungsten phosphide (CoWP), although some companies are also exploring selective tungsten deposition for this application. CoWP is selectively plated, so its cost of ownership is attractive. Continued scaling of copper interconnects is introducing problems of scattering effects, increased via resistance, copper seed layer thinning, and terminal effects associated with ohmic drop on the wafer surface.

Scientists Paul Haumesser of CEI-LETI and collaborators at Philips Semiconductors Crolles and ST Microelectronics are addressing such issues through medium-acid chemistries, planarizing copper plating, heterogeneous electrochemical reactions for barriers as an alternative to PVD, and electroless depositions of self-aligned capping layers on copper.

They also are exploring copper seed repair and electro-grafting. They reported that terminal effects could be addressed through a combination of a medium-acid, high-copper electrolyte, a deposition cell specifically designed to compensate for terminal effects (Shipley's ST3100), such as Semitool's multiple-anode CFD reactor, for a 40 nm MOCVD copper seed.

Nutool's ECMD system was used to planarize copper deposition. ALD replaced the PVD barrier, a 20 nm thick CoWP was plated on a ULK dielectric (k=2.4), and palladium activation was used to encourage highly selective deposition. However, since palladium can induce copper resistance increases, palladium-free CoWP/B or NiMoP/B barriers will be investigated in the future.

For advanced copper seed layer beyond PVD, electroless ECD with an alkaline electrolyte may be used, followed by ECD filing. The new process showed fewer bottom voids than the existing PVD process.

Electro-grafting — electrolysis of organic species (sometimes polymerizing monomers) at the electrode surface that allows deposition of conformal and adherent organic layers — is being considered for very thin barrier layer deposition. They should be compatible with electroless or electrolytic fill processes.

Another company using palladium-free CoWP processing is NEC, who's research found that alkaline-metal-free electroless plating can better meet the contamination control requirements for ULSI processing. The virtual elimination of potassium and sodium in the CoWP film and on the wafer backsides, as measured by SIMS and ICP-MS (Tables ) after cleaning are acceptable for production. However, without palladium, deposition uniformity is a challenge.

Several companies are investigating the replacement of the dielectric cap with the metal cap because of stress migration and electromigration issues associated with the known diffusion path along the copper/dielectric interface. Even with this change, however, most companies contend that the dielectric cap above will still be needed as a via etch stop in subsequent metal layers. At IITC, TSMC examined both CoWP and ALD TaN_x copper cap layers. Hsien-Ming Lee and coworkers found that ALD TaN_x cap layers improve electromigration lifetime by more than 3× through improved interface characteristics and a 5% reduction in RC delay because of the thinner cap (30 Å). Selectivity depends on the surface condition. Tantalum concentration is richer when deposited on copper than low-k dielectrics.

IBM, Chartered, Sony, AMD, Infineon and Applied Materials presented a novel copper planarization process with electrochemical mechanical polishing (ECMP) capability with lower downforce (<0.3 psi) than conventional CMP. The process was developed primarily to address the high-dishing/erosion issues associated with ultralow-k dielectrics and conventional CMP processes. In the ECMP process, bulk copper in solution is removed at a rate that depends on the applied voltage; copper is converted to Cu²⁺ + 2e^-. A physical model of the cell and current measurements and a process control algorithm controls endpoint.

The profile created by the ECMP process allows the conventional CMP process to clean remaining copper with low dishing across the wafer. Applied estimates a 30% cost reduction with this process relative to conventional copper CMP. Therefore, excessive dielectric removal for dishing correction is not necessary. The ECMP cleaner consists of a megasonic cleaning bath, two bush modules and a vapor dryer specifically designed for low-k hydrophobic films.