Wafer Provides Standard for Dielectric Test

A front-end, non-contact dielectric electrical tester is one of the process engineer's basic tools. It enables the monitoring of electrical test parameters of interest on a daily basis and supplies a warning when any parameter limits are exceeded, indicating a possible process deviation. In production, testers provide statistical process control (SPC) for critical processes, and fabs depend on them for the correct assessment of production line equipment and wafers in process.

However, partly because of a lack of good metrology, non-contact testers have not done as well as anticipated in the marketplace. Typically, a tester is more accurate than the calibration wafers being used, and the unavailability of a stable reference against which to monitor and measure its long-term repeatability sometimes leads to non-repeatable results. This can make it difficult to determine that a bad furnace monitor is a result of furnace contamination, rather than an out-of-control tester, for example.

This is a serious matter because establishing reliable tester repeatability would allow the comparison of the characteristics of high-k dielectrics and other new gate stack materials to current technologies. Key issues like interface bonding and its relationship to device reliability could be resolved in a more timely fashion, while a database line could be established for matching testers between labs, troubleshooting malfunctioning testers, and checking them after reinstallation.

Quality procedures for inspection, surveillance and monitoring of these testers have been lacking because of the unavailability of acceptable standards. The traditional tester check parameter set consists of electrical dielectric thickness (T_ox), density of interface traps (D_it), flatband voltage (V_fb) and mobile charge density (Q_m). A long-term database derived from suitable reference wafers and test methodologies would allow the engineer to isolate production problems from tester issues.

In the past, many fabs attempted to build such a database using a 600 Å SiO₂ wafer. However, its oxide was stressed to the point of parametric drift after 25 measurements, and it displayed substantial instabilities shortly after exposure to the wafer fab environment, producing inconsistent results.

A consistent test wafer would make possible the creation of a good baseline of data to work from when there is a problem. It could allow the engineer to monitor the tester's accuracy, making it a far more useful tool, and open other applications it could be used for because the tester data would then be verifiable. If the tester has problems, it can give the user an idea of what is wrong with it by allowing certain diagnostics. Before, how much the tester could be controlled was limited by how good a wafer the end user could produce.

Working with International SEMATECH and SEMI, Wafer Standards (Phoenix) has produced test wafers with a special dielectric designed to check a tester's various systems. Through the use of gate stack engineering techniques in its design and processing, the dielectric's molecular structure and its bonding to the silicon provide charges that are stable, predictable and not overly sensitive to the environment. Mobile ion measurements on an intentionally contaminated SiO₂ wafer vary between 2¹⁰ and 6¹⁰ ions/cm², which makes it useless as a standard. The new test wafer's mobile ions are confined to the top half of the dielectric and protect the underlying interface from contamination and overstress. Repeatability is 5× better on the new wafers, and all the test parameters are stable and repeatable over long periods, even with same-site testing (Figure ). The need for separate wafers for each parameter and the periodic changing of test sites is therefore eliminated.

Work with the special reference test wafers shows that critical test parameters are stable and repeatable over long periods, even with same-site testing. (Source: Wafer Standards)

The combined dielectric features of mobile ion containment and SiO₂ interface protection allow special reference wafers to be used with simple procedures for SPC and non-contact dielectric tester repair. The capability that these test wafers offer — long-term, same-site testing of dielectric parameters — provides an optimum assessment of tester repeatability and reproducibility, considerably lessening the possibility of any excursion that might jeopardize the fab line.

For additional information on inspection, measurement and test, go to www.semiconductor.net/imt