Increasing Yields for Engineered Substrates

As semiconductor manufacturing enters the sub-90 nm era, many familiar features of the CMOS process are being displaced by new processes and materials. Copper and low-k dielectric interconnects are replacing aluminum and SiO₂, reducing RC delays. New gate dielectrics and transistor structures help designers balance device speed and power consumption. Even the most fundamental material of all, the silicon wafer, is giving way to a variety of engineered substrates, from silicon-on-insulator (SOI) wafers to complex strained silicon multilayers.
 
New materials are essential if the industry is to continue its steady progress along the curve of Moore's Law. Yet new materials require new supporting technologies. Copper interconnects are not possible without copper CMP. Advanced substrates, as will be shown, demand inspection and metrology tools with greater sensitivity and higher throughput, optimized for complex film stacks.

The first engineered substrate is SOI. SOI wafers place an insulating layer, usually SiO₂, between the top silicon device layer and the bulk wafer. SOI first gained manufacturers' attention for radiation-hardened devices, as the insulating layer blocks the migration of free charges generated in the bulk. SOI wafers have come into their own, however, because the insulating layer prevents capacitive coupling between device structures and the wafer bulk and also improves isolation between adjacent transistors. Reduced parasitic effects allow SOI to achieve at least 30% improvement in transistor speed at a given design rule, equivalent to one device generation. Improved isolation reduces the risk of latch-up, allowing tighter design rules. It also cuts leakage current, reducing chip power consumption by up to 50%. Heat dissipation is now a major challenge for conventional shrinking; SOI helps chipmakers overcome this barrier.

For high-performance devices, the SOI device layer must achieve specifications comparable to those of epitaxial silicon wafers. The initial method used for manufacturing SOI wafers achieves this goal through oxygen implantation. Implanted SOI begins with a device-quality silicon wafer. Implanted oxygen forms a buried oxide layer. Annealing during and after implant consolidates the oxide layer and restores the device layer's crystal structure.

Bonded SOI wafers, in contrast, grow the insulating oxide layer directly on a device-grade wafer, then bond a second device-grade wafer on top. Early approaches to bonded SOI mechanically removed the excess silicon to achieve the desired device layer thickness. This approach, consuming two silicon wafers to produce one, was extremely expensive.

The Smart Cut layer transfer method (Fig. 1 ), developed by Soitec, considerably improves the process' throughput, enabling high-volume production. Like other bonded wafer technologies, this approach begins by oxidizing a silicon wafer. Then, a hydrogen implant through the oxidized wafer creates a line of defects located at the desired device silicon thickness. The oxidized wafer is bonded to a second "handle" wafer, then annealed. Annealing causes the defects to coalesce into hydrogen-filled cavities, splitting the bulk of the oxidized wafer from the device layer. The excess silicon is preserved intact, suitable for use as the handle for another transferred layer.

1. Process flow for Soitec’s Smart Cut layer transfer method. (Source: Soitec)

Additional complex variations on the Smart Cut theme can be used to build more advanced substrates. Many researchers are investigating the use of controlled lattice strain to improve the mobility of carriers in silicon. Strain is commonly applied by depositing silicon on top of SiGe. The silicon lattice stretches to match the larger SiGe lattice. If the strained silicon structure is built by epitaxial growth on a silicon wafer, then the rest of the device fabrication process must accommodate germanium's presence. In particular, germanium tends to diffuse into the top silicon layer at high temperatures, degrading the gate oxide and causing source/drain leakage.

The benefits of strained silicon and SOI are complementary: SOI reduces parasitic effects, while strained silicon improves transistor switching speed. The ideal structure would combine the two, placing a strained silicon layer on top of an insulator. The Smart Cut approach achieves that. By placing the hydrogen implant just below the strained silicon layer, most of the SiGe is left behind after layer transfer. What remains is easily etched away, leaving the strained silicon layer directly on SiO₂. The final device wafer contains no germanium and is fully compatible with standard CMOS fabrication.

The device layer's thickness is an important parameter in both SOI and strained SOI. The wafer may be either fully or partially depleted. In fully depleted wafers, the device layer thickness is comparable to the transistor's depletion region, typically <200 Å. In partially depleted wafers, the device layer is thicker, typically 500 Å or more.

Partially depleted SOI has been in production for several years, particularly in IBM's PowerPC chips. Fully depleted SOI is being used in some products at the 90 nm node, and is likely to become common at the 65 and 45 nm technology nodes. Some devices are using strained silicon at the 90 nm node as well; strained SOI wafers are likely to be widely used in the 65 and 45 nm nodes.

Fully depleted wafers are desirable because the thin channel helps control short channel effects. No deep well implants are needed, potentially simplifying the fabrication process. However, in fully depleted wafers, the channel dopant concentration — and therefore the device threshold voltage — depends on the device layer thickness. Current specifications anticipate a thickness uniformity tolerance of ±5%, or only 10 Å in a 200 Å layer.

To control a parameter, it is first necessary to measure it. Yet sufficiently accurate measurements of such thin stacks are difficult. Reflectometry does not have the required sensitivity and accuracy to measure and track changes in these thin films. Reflections at interfaces complicate already challenging defect inspections. Yet, even as thin layers make inspection more challenging, SOI fabrication focuses more on defectivity tracking than bulk processing, and defect inspection steps are replacing flatness inspection. The base silicon wafer, oxide layer and top silicon are critical to device performance, so each must be inspected carefully. SOI thus requires 30% more inspection steps than bulk silicon. More complex strained silicon structures will require even more inspection. The capital cost and time required by such extensive inspections make a significant contribution to overall SOI wafer cost.

Once the wafer reaches an IC manufacturing site, incoming inspection and front-end process monitoring must contend with the same challenges. With each process step, the wafer's added value increases, as does the importance of accurate monitoring.

The metrology and inspection requirements for engineered substrates duplicate those typical of bulk wafers. Defects, wafer shape and wafer flatness are as important as ever in the sub-90 nm era. Yet the multilayer structure of engineered substrates adds new parameters as well. As noted, thickness and thickness uniformity of the top silicon layer directly affect transistor characteristics. Poor interface quality, either between the bulk silicon and oxide layer or between the oxide layer and top silicon, can lead to voids and catastrophic failures. Roughness and nanotopography at either interface can affect the top surface planarity, degrading lithography and CMP performance.

The top silicon thickness for fully depleted SOI must be uniform to within 5-10 Å. To achieve control that precise, the metrology system must be accurate to within 0.5-1.0 Å. Reflectometry, often used for partially depleted SOI monitoring, is unable to measure the buried oxide and top silicon thickness separately with such thin layers, with the required sensitivity and accuracy. Instead, spectroscopic ellipsometry (SE) is emerging as the technique of choice.

SE works by shining polarized light on a sample and measuring the reflected light's change in polarization. The tool measures the amplitude ratio (tan ψ) and the phase difference (cos Δ) between the reflected light's perpendicular and parallel components. Regression analysis fits the measured values to those expected for a model stack. SE is fast, non-destructive and suitable for inline use (Fig. 2 ).

2. 3-D thickness contour maps of ~170 Å silicon on ~1450 Å oxide. (Source: KLA-Tencor)

Measuring flatness on engineered substrates is more difficult. Smaller design rules impose more demanding flatness requirements on all wafers. The very high numerical apertures needed for deep subwavelength lithography dramatically reduce the depth of focus available to the stepper. While vacuum chucking and dynamic stage tilting can accommodate large-scale topography variations like wafer bow, each individual exposure field must be absolutely flat. According to the 2003 International Technology Roadmap for Semiconductors (ITRS), the 65 nm node will require site flatness of 64 nm or better. Similarly, CMP for shallow trench isolation can leave oxide in nanometer-scale depressions, and can thin the device layer in raised areas. The 65 nm node will allow <16 nm of peak-to-valley topography variation.

In bonded wafers, thickness and uniformity at the wafer edge require especially careful attention. As manufacturers try to improve productivity, they seek to fit as many die into the wafer area as possible, and attempt to minimize the excluded zone at the wafer edge. In bonded wafers, however, beveling at the wafer edge tends to degrade the bond quality. Accurate measurements and control of the edge roll-off region are very important.

Atomic force microscopy (AFM) is the best available technique for nanometer-scale topography measurements. It scans a very fine silicon tip, only an atom or two across, over the area of interest. Surface atoms repel the tip, applying measurable force to a cantilever arm. AFM profiles the surface at the atomic level, but it is extremely slow, making substantial mapping of the entire wafer surface unfeasible.

Interferometry is usually used to map large-scale wafer geometry. While older-generation interferometers performed measurements on a vacuum chuck, newer technology suspends the wafer vertically, taking interferometric measurements of both sides simultaneously. This provides complete geometry information for the front and back side independently, eliminates vacuum chuck wafer distortion in the measurement, but preserves production throughput. Such independent back- and front-side measurements are crucial for the handle wafer prior to bonding, because the bonding process does not alter the wafer geometry. Thus, any geometry issues present in the handle wafer will appear in the finished bonded product (Fig. 3 ).

3. A typical SFQR map on a 700/1450 Å wafer demonstrates the impact of the base wafer’s properties on the flatness of the final SOI structure. (Source: Soitec)

Engineered substrates beyond SOI introduce even more metrology challenges. The performance of strained silicon transistors depends on the amount of strain in the transistor channel. SE measurements can determine the strained silicon layer's thickness even when the underlying SiGe strain layer is present. The strain in the silicon layer can be potentially determined by correlating to either the optical properties of the strained silicon layer or the composition of the relaxed SiGe strain layer.

When the SiGe layer is not present, as in bonded strained SOI substrates, strain must be measured directly from the silicon lattice. Raman spectroscopy can accomplish this, as it measures the vibrations of individual Si-Si bonds. The vibrational frequency varies with bond length. X-ray diffraction can measure the lattice constant directly, though it is best suited to large-area measurements.

Not only is surface roughness difficult to measure, it also complicates the already difficult task of defect detection. Typical defect detection systems work by scanning a laser across the wafer surface and detecting any unusual light scattering. Even on bulk silicon, defect detection becomes more difficult as dimensions shrink. For critical layers, customers need particle sensitivity of ~0.8× the layer design rule, or 70 nm for the 90 nm node, and 50 nm for the 65 nm node. Yet, a 30 nm particle scatters 20× less light than a 50 nm particle, and 100× less than a 65 nm particle. Surface roughness creates haze in optical scattering measurements, making it more difficult to detect actual particles above the background noise. After the 90 nm node, currently available defect detection systems may not meet bulk wafer inspection's requirements. SOI inspection promises to be even more difficult.

When the defect detection system's scanning laser uses visible light (488 nm), the light can reflect from interfaces within the SOI stack. Reflectivity depends on the buried oxide thickness and top silicon thickness, as well as the device surface (Fig. 4 ). The measured size of any particle depends on the measured reflectivity. Reflectivity variations with layer thickness make both detection and sizing of particles more difficult. For accurate measurements, the system must be calibrated for the appropriate stack structure. Yet each wafer user and sometimes each IC product may use a different stack structure, optimized for the requirements of a specific transistor design. Managing calibration curves for a wide range of products is complex and potentially expensive.

4. On the left is shown how incident light can scatter from both the top surface and interfaces within the SOI stack. How scattering varies with oxide and top silicon thickness is illustrated on the right. (Source: KLA-Tencor)

5. Particles trapped within the SOI structure can lead to bonding failures and holes in the top silicon layer. (Source: Soitec)

Multilayer film stacks introduce new kinds of defects as well. For example, voids in the top silicon layer are 100% yield killers, destroying any transistors unfortunate enough to land on them (Fig. 5 ). They can form when particles are trapped between the top silicon and underlying oxide, yet they are more difficult to detect than comparably sized particles. Careful particle inspection at each step in the substrate fabrication process can help prevent voids, but increases the cost of inspection.

Both scattering intensity and film thickness dependence rely on wavelength. In fact, scattering increases as 1/λ⁴; shorter wavelengths will induce more scattering from particles of a given size. Shorter wavelengths are also less sensitive to film structure, as they only penetrate part of the stack.

Since November 2003, Soitec and KLA-Tencor have worked together to develop the metrology infrastructure needed for engineered substrates. The program focuses on inspection for the 65 nm node and beyond. KLA-Tencor's Surfscan SP2 system, one product of this program, uses an ultraviolet laser (<360 nm) instead of visible light (Fig. 6). The shorter wavelength penetrates only the uppermost 10 nm of the SOI stack. Thus, a fully depleted top silicon layer gives the same response as a bulk silicon wafer. No additional calibration is required. By improving scattering from particles and reducing interface noise, the shorter wavelength achieves 250× greater scattering intensity. The sensitivity improvement allows superior throughput as well, with a 2× throughput improvement for process monitoring on bulk wafers and a 5× improvement for qualification of engineered substrates (Fig. 7 ).

6. Relative to visible light inspection (left), UV light inspection (right) nearly eliminates variations with top silicon thickness. (Source: KLA-Tencor)

Strained silicon layers typically have several orders of magnitude more defects than their conventional counterparts. The best strained silicon wafers have between 10⁴ and 10⁵ dislocations per square centimeter, compared with <1 dislocation per square centimeter in bonded SOI wafers. These arise because the relaxed SiGe layer that serves as a template for the strained silicon layer is obtained by growing a succession of buffer layers where misfit dislocations are nucleated and pinned. The buffer layers bridge the gap between the bulk silicon starting wafer and final relaxed SiGe composition (typically 20% germanium). Though misfit dislocations lie in the film's plane, they end with threading arms in the 110 plane, ending up at the upper layer surface.

7. The increased scattering intensity achieved with a shorter wavelength significantly improves inspection throughput of the Surfscan SP2. (Source: KLA-Tencor)

This relaxation mechanism induces surface undulations known as "X-hatch pattern." Like any form of surface roughness, these undulations complicate lithography and CMP; therefore, most strained silicon fabrication processes require a smoothing step to remove them.

So far, few options are available to map such high dislocation densities over the entire wafer surface. Researchers typically use selective etching to decorate dislocations and make them visible to optical microscopy. It is not clear whether this method will be acceptable for manufacturing of production wafers.

Despite the challenges, the limitations of bulk silicon and the advantages of engineered substrates give fabs little choice but to proceed with these new materials. Achieving adequate yield depends on the quality of the starting wafer and the ability of the substrate manufacturer and IC manufacturer to preserve that quality. High-throughput, high-sensitivity metrology and inspection systems, designed to accommodate the complexities of multilayer stacks, are critical for high-yield production of leading-edge devices on engineered substrates.