Inspection CoO May Be Final Barrier for SOI

At the 65 nm node, chip manufacturers will introduce a number of new materials all of which need to be cost-effectively qualified in production. "With the process integration problems that will arise from these new materials and film steps, it's likely that production yields at the 65 nm node may be reached later than expected, as occurred with 130 nm," said Mike Kirk, senior vice president and general manager of the Surfscan Division at KLA-Tencor (San Jose).

With increasing adoption by companies including IBM, Motorola, AMD, Sony and Philips, it seems that silicon-on-insulator technology is finally getting its due. However, the price is prohibitive for many applications at ~$900 per 300 mm wafer, compared with $500-600 for strained silicon, and $300-400 for epi, annealed and bulk silicon. "One of the biggest impediments to adopting SOI and strained silicon is the cost," Kirk said.

A key driver for starting wafer cost is inspection cost. Unpatterned wafer inspection is commonly used to perform final wafer certification at the wafer manufacturer and incoming quality control in the IC fab. With SOI, however, interference effects arising from multiple reflections from interfaces between silicon and buried oxide layers hamper traditional visible-wavelength wafer inspection systems, causing false and inconsistent defect readings.

KLA-Tencor's current-generation tool, the Surfscan SP1, is able to meet the 90 nm node sensitivity specification of 65 nm at high throughput. However, for the 65 nm node, the sensitivity spec drops to 45-50 nm and throughput drops to about one-quarter its previous rate. "Clearly, this reduction is unacceptable as it represents a 4× cost increase," said Wayne McMillan, senior product marketing manager for the Surfscan Division.

To qualify a process tool in the fab, the wafer is scanned, processed in the chamber, scanned again and examined for added defects. "At the 65 nm node, you need to detect defects as small as 40 nm in FEOL critical processes to avoid process tool-induced yield loss," McMillan said.

The company's next-generation Surfscan SP2 tool offers up to a 5× throughput increase, sensitivity down to 30 nm, and extendibility to the 32 nm node. It has the ability to measure defects using laser light scattering in three modes: darkfield, haze and a new surface scatter imaging technique (Fig. 1 ). Haze is the low-frequency portion of the darkfield signal, which provides a good indication of process conditions, especially surface roughness. "At the 65 nm node, angstrom-level changes in surface roughness are very important to IC makers," McMillan said. "The surface states associated with roughness are thought to impact carrier mobility."

1. The study of haze, collected as the low-frequency signal in darkfield inspection, can reveal a broad spectrum of process-induced variations, including surface roughness. Haze can also act as a proxy for other metrology tools to measure thickness, reflectivity, sheet resistance, etc. (Source: KLA-Tencor)

A new UV laser, a larger, axisymmetric collection system than the SP1, which enables increased defect sensitivity and capture rate, and the unique ability to use spatial apertures, which eliminates wafer surface noise from particular films, increase defect sensitivity and improve system performance.

KLA-Tencor worked jointly with a supplier to develop the new UV laser — one with increased illumination power and longer lifetime than the blue laser (488 nm) used in the SP1 system. The shorter UV wavelength (<360 nm) allows higher sensitivity and ~250× increase in scattering intensity for a silicon defect on a bare wafer.

Today's SOI wafers have silicon thickness ranging from 88 nm down to 55 nm, over a buried oxide layer of ~145 nm. "A key advantage of the SP2 is that a single recipe and calibration curve can be used for a given SOI process, regardless of thickness," McMillan said.

2. A shift in wavelength eliminates interference effects and makes SOI appear like polished silicon. (Source: KLA-Tencor)