Porous Low-k Materials and Effective k

By driving interconnect dimensions to ever-smaller sizes, the RC delay becomes the dominant factor to impact IC performance. The RC delay time is controlled by the resistance of the metal lines in the interconnect structure of an IC, and the capacitance between the metal lines. To reduce RC delay, copper interconnects were introduced to replace aluminum at the 175 nm generation for metal linewidths of 0.25 µm, utilizing copper's 37% lower resistivity than aluminum. The reduction of capacitance is still ongoing, and has happened in stages so far. SiO₂ (relative permeability k=4.1) was replaced by fluorinated silica (FSG, k=3.7) in the mid-90s. Currently, IC manufacturers are pushing the implementation of dense CVD SiCOH materials (k=2.7-3.0).

The most straightforward way to reduce RC delay even further — and the one most research effort is currently spent on — is to introduce porosity into the dielectric film. Dielectrics with relative permitivities of 2.5 or less can be obtained this way. Incorporating fluorine in large amounts into the material, which lowers k by reducing the atomic polarizability, is also being worked on, but is plagued by delamination and fluorine bond stability issues. The lowest k values obtained so far by introducing porosity into thin methyl silsesquioxane (MSQ)-based or organic films are ~1.6.

Porosity causes the mechanical, thermal and chemical properties of the materials to deteriorate. The porous materials are susceptible to chemical modifications in aggressive environments, such as during etch and resist strip. Modulus and hardness are significantly lower for porous materials compared with their dense counterparts, which can lead to cracking and delamination problems. Finally, the thermal conductivity can be very low (10-20% of the value of SiO₂ is typical), while the coefficient of thermal expansion (CTE) can be very high (several times that of copper is not unusual).

These adverse properties force a number of advanced processes and integration schemes. For example, special cleans of the substrate or an adhesion-promoting layer are used at the bottom interface of the porous film to avoid delamination problems. To improve adhesion at the top interface, the porous film is often densified prior to the deposition of the next film. To prohibit barrier metals or copper diffusion into the porous material, special sidewall liners — sometimes dielectric ones — are used. These additional processes not only increase the cost per metal level significantly, but also tend to increase the line-to-line capacitance. Ultimately, the advantage gained by introducing porous low-k dielectrics may be offset by necessary integration trickery and undesired processing effects. Some of these adverse effects and their impact on intra-line capacitance are described in this article.

Effective k simulations

1. Definition of the effective dielectric. The films in which the metal line (red) is embedded (etch stop, bulk dielectric, hard mask and cap) are combined, in the model, into the effective dielectric (yellow). Other dielectric films (blue and green) are included in the model. The error of keff extraction with this model is reasonably low — about ±4%.

Capacitance simulations are used to extract the effective relative permittivities of existing interconnect structures, or to make predictions about the k value of structures that use different materials and/or different feature sizes. For the purpose of this work, the effective k value (k_eff) is defined as in Figure 1 . In the model, one effective dielectric takes the place of the bulk low-k, and the dielectric thin films below and above the metal line (such as the etch stop, hard mask and cap). To extract k_eff, the capacitance between two interdigitated combs is measured. Then the dimensions of the comb (dielectric layer thicknesses and metal line shape) are obtained from cross-sections, and entered into the model. The output of the model is matched to the measurement by varying the k value of the effective dielectric.

For a typical comb structure, built in a damascene scheme with a porous MSQ-based dielectric of relative permittivity k=2.3, k_eff is 3.1 ±0.1. This structure includes a CVD SiCN etch stop (1000 Å), hard mask (200 Å after CMP) and cap (500 Å), all of which have k=4.3. Typically, k of an integrated porous film is significantly higher than that of the untreated blanket film because of densification and composition changes during processing.

To achieve good adhesion of the hard mask to the dielectric, it was necessary to plasma-densify the porous film prior to hard mask deposition. During trench etch and resist strip, the dielectric along the trench sidewalls is densified and depleted of carbon. The k value of the sidewall region is increased because of the increased number of polar bonds in the oxygen-rich film, and because of moisture uptake. This causes the undesirable effect shown in Figure 2 : Damaged material fills a larger fraction of narrow spaces between metal lines compared with wide spaces, causing k_eff to increase for small spaces. According to Figure 2 , k_eff for a typical porous MSQ-based material increases by 10% when the pitch is reduced from 600 to 400 nm (corresponding to a reduction of the spacing between metal lines from 260 to 170 nm). Also shown in Figure 2 are extracted effective k values for dense SiO₂ and an alternative porous low-k material family. As expected for dense SiO₂, k_eff is constant with respect to the width of spaces between metal lines. Also, the alternative material, integrated in a significantly different way, has a constant k_eff, indicating a negligible amount of sidewall damage.

2. Results of keff extractions for different dielectric materials. For low-k #1, keff increases by ~10% as the pitch shrinks from 600 to 400 nm, indicating significant sidewall damage. The two curves represent two identically processed wafers. Some other materials are included for reference. Dense SiO2 yields keff of ~4.2, with no dependence on pitch. Another low-k material family (#2) also shows no change in keff, indicating significantly less sidewall damage than material #1. Finally, replacing the SiN cap with SiCN lowers keff by ~0.2.

Process variations could reduce k_eff. It is feasible, for example, that a change to etch and resist strip chemistries could result in less damage to the porous dielectric, thereby lowering k_eff. Work by different groups, however, has shown that damage to porous materials occurs for a wide range of gaseous or wet treatments, making a certain degree of damage an unavoidable reality. It becomes obvious that different integration approaches or different dielectric materials are needed to achieve the International Technology Roadmap for Semiconductors (ITRS) target of 2.3-2.6 for the effective relative permittivity of interconnects in the 45 nm node.

Various changes to the integration scheme can be applied to achieve lower k_eff. CVD etch stop layers, hard masks and caps, which typically have k=3.9-4.3, can be replaced with lower-k materials. Dense CVD oxycarbide films and dense MSQ-based spin-on materials have k=2.7-3.0. Another approach is to reduce the thickness of these layers, or even to eliminate them. Etch stop layers, for example, can be avoided in hybrid integration schemes, in which the via and line dielectric of a dual-damascene level are chemically significantly different materials, such as organosilicate glass (OSG) and organic polymers. If via and line level use the same dielectric, the etch stop layer can be omitted if the etch processes are optimized to minimize across-wafer non-uniformity and microtrenching of trench bottoms, and if a feedback loop for the trench etch time is provided.

Each of these integration changes poses its own set of problems. Most notably, new low-k etch stops and hard masks may have higher etch and polish rates than CVD carbide and oxide films, thus requiring costly material selection and process development. It is therefore desirable to evaluate the impact of changes to the integration scheme on k_eff through capacitance simulations, rather than committing large resources to multiple attempts at process development and integration.

The starting point for these simulations is a capacitance measurement, typically from two inter-digitated combs. This capacitance is first matched in a simulation for k_eff, as described in Figure 1 . Then the capacitance of the same structure is simulated using a second model that contains each individual layer (etch stop, low-k dielectric and so forth), rather than combining them into an effective dielectric. The change one is interested in is then applied to this model, which will change the simulated capacitance. Finally, the k value of the effective dielectric in the first model is changed so that the capacitance of this simulation model matches that of the changed structure. The result of this matching procedure is the k_eff one can expect from the changed integration scheme.

Some results of this analysis are shown in Figure 3 , where k_eff is plotted as a function of the k value of the bulk dielectric after integration. The starting point (baseline) used for this analysis is a dual-damascene integration scheme with a porous MSQ-based spin-on dielectric used for both via and line level. A rather thick CVD SiCN etch stop (100 nm) is employed. The level is capped with 50 nm of the same material. The k_eff of this structure, determined by extraction from a comb at 550 nm pitch, is 3.1 ±0.1, and the k value of the porous dielectric after processing is 2.4 ±0.4.

3. Simulations predicting the change of keff for different dielectric film stacks. Solid squares: The baseline consists of a thick (100 nm) CVD SiCN etch stop, the bulk low-k (350 nm, k=2.4 after processing), and a CVD SiCN cap (50 nm). Open triangles: Cap and etch stop are a dense MSQ-based spin-on film (k=2.8, same thickness as in baseline). Open squares: Etch stop is replaced with bulk dielectric. Open circles: Thickness of the etch stop and cap is reduced to half of their baseline values (CVD carbonitride). Reducing the k value of assist layers is significantly more efficient than thickness reduction.

Figure 3 shows that significantly lower effective k values are obtained for modifications to the stack. Thinning the etch stop and cap to 50% of their baseline thickness reduces k_eff to ~2.9 for the same bulk dielectric. It is more effective, however, to reduce the k value of these assist layers: When the CVD etch stop and cap are replaced with spin-on films of the baseline thickness and k=2.8, for example, k_eff drops to <2.6 for the same bulk dielectric (i.e., low-k remains the same at 2.4). Since surface densification of the bulk dielectric is not needed for adhesion improvement in the case of spin-on caps, the k value of the bulk dielectric will be somewhat lower, causing k_eff to drop even more.

Also included in Figure 3 are expected k_eff values when the ES layer is omitted entirely as the only change to the baseline. For the same bulk dielectric (k=2.4), k_eff will be reduced to ~2.7. It is interesting to note that the original k_eff of the unmodified stack could have been obtained also by using a dense dielectric film with k=2.8, such as a CVD SiCOH, and no etch stop. This would eliminate problems caused by the insufficient mechanical and chemical properties of the porous ultralow-k bulk material.

Capacitance simulations were also used to make predictions of k_eff values at dimensions relevant to the 45 nm technology node, and to determine the impact of damaged trench sidewalls on k_eff at these smaller ground rules. Estimates about the thickness and k value of the damage region can be obtained from electron energy loss spectroscopy (EELS) and Figure 1 . In EELS concentration profiles, carbon and oxygen show variations to a depth of ~20-25 nm from the sidewall, which serves as an estimate for the thickness of the damaged layer. A k value of 3.8 is a lower boundary for the k value of this damaged layer.

4. Predicted keff values at the 45 nm node (70/70 nm line/space width) for the baseline (solid symbols), and an improved integration scheme (open symbols). The squares show k values in the absence of sidewall damage, and circles represent keff with sidewall damage. At this feature size, sidewall damage increases keff by ~16% at a bulk k=2.3 (vertical arrow). A dense bulk dielectric with k=3.0 and negligible sidewall damage will yield a lower keff (tilted arrow).

Figure 4 shows predicted k_eff values for line/space widths of 70/70 nm. The models were obtained by shrinking the model of Figure 1 to dielectric film thicknesses and linewidths appropriate for the 45 nm node. The baseline stack consists of an etch stop layer (50 nm, k=4.3), bulk dielectric (150 nm), and a cap (50 nm, k=4.3). When the damaged sidewall is superimposed on the model, the capacitance and k_eff of the structure increase. For the baseline, the presence of the sidewall damage region increases k_eff from 3.07 to 3.56 at k=2.3 for the bulk dielectric, an increase of 16%. In contrast, for the large-pitch model of Figure 1, k_eff increases by only 2.9% if the same damaged sidewall is superimposed. A dense bulk dielectric with k=3.0, which can be processed with no significant amount of sidewall damage, would yield a k_eff of ~3.49 for the baseline integration scheme — slightly better than the value obtained with the porous bulk dielectric and damaged sidewalls in the same integration scheme.

Also shown in Figure 4 are predicted k_eff values for an improved baseline, in which the CVD etch stop and cap is replaced with lower-k materials (such as dense spin-on MSQ films with k=2.8), and the cap is thinned to 26 nm. These changes cause k_eff to drop by >18%. However, if the damaged sidewall is superimposed on the model, almost all the benefit of the improvements is lost.

The predictive k_eff simulations show that sidewall damage can no longer be neglected in development work for the 45 nm node. The etch and strip processes currently employed cause modifications to the dielectric that nullify the benefit of introducing porosity to features with dielectric spacers of 70 nm or less. It will be necessary to pick materials with minimal chemical susceptibility, and to develop new etch and strip processes that cause less damage.

If this selection process continues to be slow, IC manufacturers will switch to different materials for the 45 nm node: Dense materials with k~3.0, which can be integrated with significantly less sidewall damage, can yield similar k values as porous films. Dense films with large amounts of fluorine offer low k values (<2.2) and the possibility of avoiding sidewall damage, but are struggling with their own integration problems, such as delamination. Finally, air gaps and late-burn-out schemes could be employed.