Advanced Process Control Comes of Age

Wafer processing has traditionally depended on a series of localized regulatory controllers to assure process consistency. The idea of a supervisory controller, historically portrayed as part of advanced process control (APC), has been the source of hotly contested debates as its very definition is being developed. APC manifests itself in various forms: from the passive collection of process and wafer data to tool-to-tool process adjustments and from self-aware tools to manufacturing execution system (MES) enabled implementations. Despite the evolving nature of APC, the industry is pushing ahead. The continuous shrink of circuit device features and larger wafer sizes have made wafers more valuable, thereby driving the increased demand for some form of APC.
 
Recent advances in metrology — particularly smaller form factor — have made possible the integration of metrology systems on process tools. This has enabled the industry to increase wafer pre- and/or post-process inspection frequency, helping mitigate the risk for scrap or yield loss. Some semiconductor processes and applications are already on the cusp of justifying the added cost for integrated metrology (IM). A good example is CMP,¹ which — because of its inherent process characteristics — has been one of the early adopters of IM to monitor film removal and uniformity. Pre- and/or post-polish measurements are being used to compensate for both incoming film thickness variation and process drift. Another example is polysilicon gate etch,² where the resulting linewidth has a direct correlation to device performance. Post-litho/pre-etch CD measurements are being used to adjust etch trim time and effectively compensate for lithography CD variability. In fact, in this specific case, the combined litho/etch/IM/APC system not only improves post-etch CD wafer-to-wafer variability, but extends the patterning capability to deep subwavelength gate lengths that are virtually impossible to optically print.

IM units provide relevant measurements at critical process steps. Once the data is collected, it must be stored, transported and analyzed before IM's value can materialize. As the wafer monitoring frequency and number of measurements per wafer is increased, the amount of data grows exponentially and data management becomes imperative. For these reasons, the success of IM rests largely on APC and e-diagnostics.³

In a manufacturing flow, each process step contributes to the end product's variance. A variational sensitivity analysis helps identify the process steps where IM and/or some form of APC can benefit the overall quality of the process flow. Electrical test data, being the ultimate line metric, is the pivotal factor in deciding which steps to target. Here, we have focused our attention on several APC applications that have been shown to benefit a back-end-of-line (BEOL) process flow in terms of process Cp and Cpk improvement, device yield management and flexibility of the manufacturing process.

For our study, the APC approach we used was model-based and employed a run-to-run control methodology to automatically adjust the recipe based on data from the process, previously processed wafers and incoming wafer variability. Post-process validation of the controller's quality was performed to offer assurance that the flow was within specifications. This is typically required for most run-to-run applications. With the advent of IM, the effect has been a catalyst to the deployment of APC on a wafer-to-wafer basis since it enables shorter cycle times.

The combination of the process tool, inline metrology and APC can help achieve wafer-to-wafer uniformity and on-target processing. When implementing APC on a wafer-to-wafer basis, actual wafer flow within a tool (FOUP, loadlock, transfer chamber, process chamber, inline metrology, etc.), timing for recipe adjustments, and measurement frequency are a few of the critical factors that must be considered. However, to get the value out of implementing run-to-run vs. throughput considerations, it is important to determine the amount of data required — measurement frequency, sequence, for example — for a viable metrology strategy.

A design of experiments (DOE) was performed to understand the interactions, parameter sensitivity and tolerance for the critical steps. Data collected from the DOE was then used to construct a model, which was validated against the run results. Once the process model was developed, we used it to predict the optimal combination of manipulated input variables to achieve the target of the controlled outputs. If the measured output results did not match the predicted values, feedback was triggered to correct for the next wafer. Tool performance was therefore a function of previously run wafer measurements, the state of the incoming wafer, and the current state of the tool.

We assigned weights to both manipulated and controllable parameters to account for relative priority and tolerance, respectively. Tool dynamics were maintained on a device-specific format so that multiple products could run continuously and in parallel. This feature is particularly important in a foundry environment, where a multitude of products are processed on the same tool.

The APC system had a series of precautionary features, such as user-configurable safety nets and error notifications. Boundary conditions were set on manipulated parameters to prevent the APC optimizer from adjusting process recipes beyond an operator acceptable domain. When an error was sent to the tool, it alerted operators and interrupted wafer processing until an operator allowed them to resume.

Traditional lot-to-lot process control monitors wafers after processing using external metrology tools, but does not provide a rapid response back to the process system, potentially allowing some wafers to be scrapped. Wafer-to-wafer control provides a compromise solution, since wafers can be monitored as they exit the processing tool and adjustments rapidly made to the process for incoming wafers. In this case, IM is of critical importance to achieve quick feedback of any process variation or excursion.

As technology moves from the 130 nm node to the 100 nm node, the required process control limit becomes tighter and more stringent. Implementation of IM and a robust APC maintains the stringent control limits determined by the process capability, enabling any process drift or excursion to be captured and corrected in real time to minimize the yield loss.

For IM to function in a manufacturing environment, it must be accurate and robust. Since run-to-run control is executed based on the output from the metrology, if it is not accurate or repeatable, control and feedback could lead to totally unintended outcomes. In addition, the metrology strategy needs to be defined such that it can measure production wafers without constraint.

The BEOL process flow was composed of the following toolset: CVD, litho, etch, PVD, ECP, CMP. The flow itself was based on a number of steps that included dielectric deposition, trench and via etch, barrier/seed, copper electroplating and CMP (Fig. 1 ). Since up to nine levels of metal are required at the 130 nm node, dual-damascene processing makes up the predominant number of wiring levels required in BEOL processing. To expedite learning, we used a two-copper-level interconnect to evaluate process parametric yield and integration issues. The M1 level was fabricated with a single-damascene approach, and the V1 and M2 were fabricated together using the preferred dual-damascene via-first integration scheme. In this integration scheme, the vias are patterned first, followed by the patterning of the metal troughs that will be filled with metal. This approach does not suffer from the topography of a trench-first integration approach, which can limit the via lithography depth of focus.

1. In the study, the BEOL process flow was composed of CVD, litho, etch, PVD, ECP and CMP toolsets. Flow steps included dielectric deposition, trench and via etch, barrier/seed deposition, copper electroplating and CMP.

Since many steps in the damascene process flow are interrelated, APC of individual unit process was essential, but not adequate. Multiprocess control, or tool-to-tool control, with data feedforward and feedback, would further improve the overall process control and yield. In addition, this high level of control should offer the capability to accomplish the tool-to-tool matching when multiple tools are used for processing in a high-volume manufacturing environment. There are multiple opportunities to implement data feedforward/feedback control within different damascene process steps.

We focused on and demonstrated improvements achieved when APC is applied as part of our BEOL flow, copper/low-k. Feedback and feedforward strategies were used to improve wafer-to-wafer uniformity, and its impact on actual electrical test data — as the ultimate figure of merit — will be demonstrated.

In dual-damascene applications, one of the most critical steps is dielectric deposition, since it can affect level-to-level capacitance and via open yield. By measuring film thickness on every wafer, process variations between tools and between chambers were eliminated by adjusting for appropriate process conditions. An integrated optical spectrometer/reflectometer was used to make multiple point measurements of film thickness for each wafer following dielectric deposition. The recipe specified measurements to be taken over copper pads, which provided the required substrate reflectivity. These thickness measurements when combined with an APC feedback loop assured on-target wafer thickness.

Figure 2 shows the performance of two different tools run with and without APC. The wafer-to-wafer thickness uniformity for both tools when run in open loop was 1.36%, which resulted in a Cpk of 0.79. When the feedback control was activated, wafer-to-wafer thickness uniformity improved to 0.70%, which gave a Cpk of 2.15. The controller was able to maintain the target thickness throughout the entire run for both tools.

2. The difference in tool performance when run with and without APC is readily apparent. In this case, wafer-to-wafer thickness uniformity for both tools when run in open loop was 1.36%, resulting in a Cpk of 0.79. With feedback control, wafer-to-wafer thickness uniformity improved to 0.70%, providing a Cpk of 2.15. The controller maintained the target thickness throughout the run for both tools.

The impact of incoming thickness variability during via etch can be detrimental to via chain resistance. Incoming thicknesses that are less than nominal can cause barrier punch-through (which can lead to copper sputter) and greater than nominal — in extreme cases — can cause closed vias. Managing barrier loss during via etch is of great importance. To test the improvements gained during via etch when etch time is adjusted based on incoming via stack thickness, a number of wafers were deposited with films at varying thicknesses off nominal (±400 Å max.). These wafers — with varying film thicknesses — were sent for via etch processing. One set of wafers was etched with a fixed etch time while, for the other, etch time was adjusted based on the incoming via stack thickness. The wafer-to-wafer variation of via resistance was improved from 2.94% to 1.82% when feedforward was activated. The improvement comes primarily from wafers with >300 Å dielectric thickness. As seen in Figure 3 , adjusting for incoming via stack thickness delivers a tighter via chain distribution.

3. Adjusting for incoming via stack thickness results in a tighter via chain distribution.

By using the thickness measurement after dielectric deposition, the thickness data was fed forward to the etch system to optimize via etch time for each individual wafer. This enabled us to achieve tight process control of the via etch and effectively reduce the required selectivity of the etcher. In turn, this led to a reduction of the required barrier thickness, and lowered the effective k of the dielectric film stack.

The impact of tool/chamber mismatch for dielectric deposition on electrical performance is clearly illustrated in Figure 4 . A left-to-right mismatch in a twin chamber can result in a level-to-level capacitance distribution that is bimodal. By activating APC for both sides of the twin chamber, it is brought back on target, and the level-to-level capacitance is reduced from 19.3% to 5.7%. By using APC, we were able to handle the mismatch without a problem.

4. Impact of tool/chamber mismatch for dielectric deposition on electrical performance is very apparent in these graphs. A left-to-right mismatch in a twin chamber can result in a bimodal level-to-level capacitance distribution. The application of APC for both sides of the twin chamber brings the process back on target, reducing the level-to-level capacitance from 19.3% to 5.7%.

APC techniques have gained industry-wide acceptance over the past few years and are rapidly appearing in leading-edge semiconductor production facilities. APC has become a critical element for 130 nm and below copper device manufacturers. It has been demonstrated to reduce process variations while improving yield, productivity and flexibility through run-to-run, wafer-to-wafer and within-wafer control.

The "closed loop" between onboard metrology and the process control algorithm enables real-time process control that accommodates the tighter tolerances associated with high-performance devices. One of the main advantages is that it keeps the deposited thickness on target even in cases where the deposition rate is changing mildly. The wafer-to-wafer variation for FSG deposition that seriously affects the level-to-level capacitance and the via chain resistance distribution and, in extreme cases, the via chain yields, can be greatly improved by APC feedback/ feedforward control. The APC approach described delivers excellent process benefits while maximizing productive tool time and minimizing overall monitoring costs.