Back-End Executive Outlook

Semiconductor International asked some of today's leading industry executives to give us their outlook on what they're expecting to see at SEMICON West 2004. Key trends in packaging and test are presented in the following section. Front-end trends are presented separately.

John Macrina
Group Manager, Microelectronics, Panasonic

The move to the 45 nm node simultaneously combines many processing changes to meet the RC (resistance capacitance) delay. To achieve the feature sizes, along with copper metallurgy, ultralow-k dielectrics will be required. Cost-effective processing through reflow furnaces now has to be reviewed to determine its viability. In some cases, local reflow will be required to more closely control thermal processing. Mechanical properties of the die have changed dramatically to lower the forces allowed for dicing and die bonding/flip-chip bonding. Additionally, placement force must be closely monitored and reduced if needed.

To prevent die damage or delamination prior to singulation, non-contact/non-mechanical scribing of the wafer may be required. A good alternative is laser scribing, which has proven itself today in high-volume manufacturing. Die stack material must be considered when determining which laser to use and in what configuration. To ensure the best match to the die stack, laser properties must be considered as well, including repetition rate, pulse energy, and pulse type. Recipe settings will then be needed to control proper kerf width and cut depth. These settings include projection optics, collimator settings and pulse width.

In certain packages, thinning of the die is required for stacking to meet functionality needs. Most of the initial thinning will be limited to low-density devices (LDI) not requiring low-k materials. LDI products require 50-100 µm thin die packages. Thinning will add some new steps to the assembly process after receiving the wafer from the front end. The backgrinding process has to define die stress relief to eliminate fallout due to cracked die and yield losses. The stress induced by the backgrinding process must be relieved before the wafer can be further processed if high yields are to be expected.

Die bonding/flip-chip bonding must keep in line with these new challenges. Tools must now incorporate the capabilities of handling both thin die and low-k requirements, including copper metallurgies. Thin die requirements change handling requirements, and care must be taken while moving the die from the wafer frame to substrate, all while improving throughput. New or modified die ejectors must now handle existing or UV-sensitive tape to remove the die, while the bonding head and flip head must be able to transport this flexible die to the bonding site. Once at the bonding site, the bond head must be able to evenly distribute bond forces within recipe parameters.

The flip-chip market is growing as expected. However, growth must be logical and based on solving real needs. Drivers for the market are electrical performance and thermal management. Higher-frequency devices are moving to flip-chip for improved electrical properties. For higher-density and high-power devices, heat dissipation is required. Overall, the move to flip-chip must be cost-effective, driven by performance, and reliable. Additionally, the move must be easy to implement in concert with other industry drivers, such as the lead-free initiative, low-k and no-flow underfill. More and more, the answer is metal die bonding (MDB). MDB comes in several forms, the most common being gold-to-gold interconnect (GGI). Others include the encapsulated solder connection (ESC) process. These processes answer the key drivers and solve the primary concerns of keeping costs low.

Alec J. Babiarz
Senior Vice President, Asymtek, a Nordson Company

Flip-chip demand continues to increase in semiconductor packaging. In fact, the demand for machines for underfilling is now 10× that of dam and fill operations, from the perspective of a supplier of advanced packaging equipment. Flip-chips are used in several growing applications, including high-performance large die (>9 mm) and chip-on-flex for disk drives. There is also a growing trend for small (>2 mm) flip-chips requiring underfill. In new applications of small and medium-sized flip-chips, no-flow underfill materials are also growing in popularity.

One key machine in flip-chip assembly is the dispensing system, which applies both standard underfill and no-flow underfill materials. Dispensing has traditionally been done using needles, but new technologies, like non-contact jetting, are improving the process as well as enabling the use of new types of semiconductor packages in product designs.

Jetting underfill produces at least 2× the throughput over needle dispensing because the jet delivers more fluid to the part in a narrower stream than is possible with a needle — more material can be applied in a single pass. In addition, the jet produces smaller wet-out areas and fillets than possible with needle technology. These advantages all accommodate tighter design rules on packaging, enabling smaller packages.

The trend to use flip-chips in all processors, graphic chips, and other high-performance applications has now become an established practice. The new trend is the continued expansion of flip-chip applications into stacked die, memory, area array line drivers, and other traditionally wire-bonded packages. This trend is enabled by new underfill materials and jetting technology that produce a flip-chip package smaller in design at a lower cost.

Elvino da Silveira
President and CEO, Azores Corp.

Wafer-level packaging (WLP) is becoming more prevalent in the semiconductor packaging industry, fueled by the increasing prominence of area array devices in electronics manufacturing. Traditional wafer bumping processes have been based on stencil printing techniques or digitally driven jetting technologies. However, there are significant limitations to these processes, the most important being limitations on bump size within the parameters of precision and repeatability.

With current feature size requirements shrinking, wafer bumping can best be accomplished by either a photolithography stepper or proximity mask aligner. A key factor in this decision is the financial capabilities of the manufacturer and the relative process/cost benefits of photolithography. To make this decision, manufacturers must weigh the relative performance capabilities, throughput, and process flexibility of photolithography.

Peter Bierhuis
President, March Plasma Systems

The accelerated business levels that began in 2003 and are continuing into 2004 confirm our earlier prognosis of a continued focus on yield and reliability. Manufacturers are investing in precision equipment to ensure high-quality production of smaller-geometry and increasingly complex packages that represent higher-value components. In addition, new material introductions pose manufacturing challenges that are driving requirements for contaminant-free surfaces.

New package technologies, such as stacked die, QFNs, system-in-a-package (SiP) and flip-chip, are stimulating major packaging equipment investments. We are finding an increased interest, although still limited in volume, in wafer-based applications.

Keith Lee
CEO and President, Advantest America Inc.

Overall, the industry is realizing recovery across all segments and, though long-term visibility is somewhat limited, we do believe that 2004 will remain strong. Increases in both consumer and corporate spending are providing the impetus for the current upturn. On the applications side, fueling what appears to be an insatiable appetite for electronic gadgetry, we see increased demand for microprocessors, chipsets and digital consumer devices such as cell phones with built-in cameras, digital camcorders, DVD players and video game consoles. This activity, in concert with a rise in corporate IT spending on replacement PCs and wired/wireless network equipment, is creating a robust environment.

The emerging trend toward customized chips will require specialized packaging and tester interfaces, giving opportunity to manufacturers of turnkey solutions. And, as product miniaturization also gains in popularity, we expect that an increased use of stacked chips will present added and more complex testing requirements.

In the test arena, we see memory testing growing briskly in 2004, as both the DRAM and flash memory markets experience solid growth, as well as the still relatively small CMOS image-sensor market. In the system-on-chip (SoC) and ASIC tester markets, strong sales are expected to continue for testers targeting digital consumer devices, microprocessors, microcontrollers and LCD-driver ICs. Design for test (DFT) and built-in self-test (BIST) are here to stay as methods to control the cost of testing increasingly complex devices. The move toward an open, standardized architecture for testing will intensify, as customers become aware of the flexibility and cost advantages of a modular reconfigurable ATE platform.