Roadmap Challenges Underscore Troubling Trend in Yields

For the last several technology nodes, SEMATECH work has shown that mature yields have been declining, so at some point in time we're either going to have to lower the target, or perhaps extend the time between technology nodes, in order to resolve these yield problems," commented Fred Lakhani, senior member of the technical staff at International SEMATECH (ISMT, Austin, Texas). In an interview with Semiconductor International, Lakhani said that mature yields are not reaching traditionally high levels, even though yields are ramping faster, primarily due to the introduction of products at earlier stages.

Lakhani and colleagues mapped out the Yield Enhancement portion of the 2003 ITRS, which highlights the growing importance of systematic mechanism-limited yield and non-visual defects, and it calls for better data management and significantly faster defect isolation strategies. Also, high aspect ratio inspection (HARI) continues to be a grand challenge.

The causes of the lower mature yields are multiple and varied. The introduction of new materials has led to new integration problems and failure mechanisms. Process flows are getting longer, which reduces the number of yield learning cycles. Just at the interconnect levels, multiple low-k dielectric films in a given level are not uncommon, and often use hard mask or sacrificial films. The industry is losing more die to non-visible defects than in the past — defects that leave no detectable physical remnant. One example is a crystalline defect in strained silicon that causes a transistor parametric problem.

Though the industry has always been aware that the overall yield is a product of the random defect-limited yield and systematic mechanism-limited yield, improvement strategies have traditionally focused on the random component — mostly targeting contamination in processes, materials and the environment. Now the systematic problems require more attention, but not at the expense of random defect reduction efforts.

Though random defects are successfully modeled using the negative binomial model or comparable models, modeling the systematic component is more complicated. In early stages of ramping, systematic mechanisms tend to limit yields, including parametric issues and design-to-process mismatch issues. "Systematic defect mechanisms can be introduced from design, process or test; basically anything with spatial or time-based signature can be considered systematic," Lakhani said. Potential yield modeling solutions (Figure ) must account for the influence of line-edge roughness, thin-film integrity and non-visual defects.

Several approaches that may prove effective in improving the modeling of both random and systematic mechanism-limited yields. (Source: 2003 ITRS)

With integrated metrology (IM), the industry juggles measurement sensitivity and tool throughput. Even with recent advances in metrology tool speed, the ultimate solution — achieving simultaneous greater sensitivity, higher sampling rate, high throughput and faster classification of defects — will require out-of-the-box thinking, Lakhani said. Device manufacturers also struggle with cost. IM tools are needed, but they have reduced sensitivity relative to state-of-the-art standalone tools. So the chipmakers end up spending more to have both the IM and standalone tools available. "It's an interesting dilemma. But experts agree that APC is the way to go and integrated metrology has to fit into that strategy."

For additional information on yield management, go to www.semiconductor.net/yield