Intel Unveils 65 nm Technology

Intel Corp. (Santa Clara, Calif.) has built fully functional SRAM chips using 65 nm technology, its next-generation high-volume semiconductor manufacturing process. Intel said it is on track to put this process into production in 2005 using 300 mm wafers.
 
This new 65 nm process combines higher-performance and lower-power transistors, a second-generation version of Intel's strained silicon, high-speed copper interconnects, and a low-k dielectric material.

The process will feature transistors measuring 35 nm in gate length, which Intel says will be the smallest and highest-performing CMOS transistors in high-volume production. By comparison, the most advanced transistors in production today measure 50 nm. Intel has integrated a second-generation version of its high-performance strained silicon into this process. Strained silicon provides higher drive current, increasing the speed of the transistors with only a 2% increase in manufacturing cost. The process integrates eight copper interconnect layers and uses a low-k dielectric material that increases the signal speed inside the chip and reduces chip power consumption.

Intel has used its 65 nm process to make fully functional, 4 Mb SRAM chips with a very small 0.57 µm² cell size. Small SRAM cells allow for the integration of larger caches in processors, which increase performance. The SRAM cells have robust operating characteristics, with a solid noise margin indicating very efficient on/off switching properties. Each SRAM memory cell has six transistors.

"Intel's 65 nm process development is progressing well, and we are producing these wafers and chips in our development fab," said Mark Bohr, Intel senior fellow and director of process architecture and integration. "By 2005, we expect to be the first company to have a 65 nm process in manufacturing."

The 65 nm semiconductor devices were manufactured at Intel's 300 mm development fab (called D1D) in Hillsboro, Ore., where the process was developed. D1D is Intel's newest fab and contains its largest individual cleanroom measuring 176,000 ft².

For additional information on wafer processing, go to www.semiconductor.net/wafer