The ITRS Roadmap for Packaging Semiconductors

The latest update of the International Roadmap for Semiconductors (ITRS) was released in December. The Assembly and Packaging portions of the roadmap provide insights into industry needs for 2004 and years beyond.

The first observation from this segment of the roadmap document is that of "increased awareness" surrounding the role for assembly and packaging and its impact on the final semiconductor product. In fact, the document crafters cite assembly and packaging as a competitive factor affecting operating frequency, power, complexity, reliability and cost. Further, they state that technology boundaries between semiconductor technology, packaging technology and system technologies have become blurred to the point that package designers cannot operate independent of chip and system designs, but rather must engage in concurrent engineering efforts.

For single-chip packaging technology, the roadmap observes that, while assembly and packaging cost per pin will continue to decrease over time, the current pincount explosion is increasing more rapidly than cost is decreasing, while at the same time also adding substrate and system-level cost. Thus, long-term packaging advancements will require affordable technology solutions beyond the current pincount parameter.

Package design requirements include physical, electrical, thermal, mechanical, assembly and manufacturability considerations, plus cost and availability. Co-design with chip design is the suggested ideal solution. Thermal management solutions include materials with higher thermal conductivity, reduction in internal thermal resistance, and novel design approaches that seek to manage cooling.

Perhaps the most dramatic improvements will need to come from new materials to support the projected technology nodes driven by semiconductor requirements in power, frequency and I/O, coupled with market demands in cost, size, weight and environments (Table ). Packaging will be forced to reduce wire bond pitch, requiring a corresponding reduction in wire size, capillary and solutions for wire sweep, electrical signal integrity and bond pad design — all imposing significant material upgrades and process innovation.

Other material issues include a projected reduction of flip-chip bump pitch from 150 to 100 µm, and the introduction of copper/low-k materials. Electrical-thermal migration in the solder UBM structure and underfill void/adhesion seriously challenge flip-chip, while copper/low-k on-die dielectric stiffness poses thermomechanical stress issues to the die/package interface, especially given the rise of die stacking for mainstream applications. Further material challenges are environmental issues with lead-free solders and halogen-free material development and implementation.

Reliability concerns center on the introduction of so many new package formats in interaction with the aforementioned new materials and heightened environmental awareness. Extensive characterization, intensified simulation and more emphasis on physical and thermomechanical models will be deployed for validation. Conception and development of new tools, in conjunction with expansion of existing X-ray, acoustic and Moire technologies for package fault isolation must address major issues such as alpha radiation, interfacial delamination, coefficient of thermal expansion (CTE) material mismatch and electrostatic discharge (ESD).

The ITRS refers to system-in-package (SiP) as, "the fourth wave of packaging innovation," suggesting a revolutionary breakthrough propelled by portable, wireless applications. Emerging as an alternative to system-on-chip (SoC), SiP combines semiconductors, passives and interconnects in one package, enabling higher system integration.

Some key packaging solutions foreseen by the ITRS include wafer-level packaging, chip-to-next-level interconnects, BGAs, fine-pitch BGA/chip-scale packages, and high-density package substrates and PCBs. Of these, wafer-level packaging represents the greatest likelihood for breakthrough potential, since it leverages economy of scale, but presently it lacks full development of wafer-level test and burn-in technologies. The other solutions will offer practical extensions of existing technology and should see near-term rapid growth.

The ITRS is a worthwhile document charting semiconductor technology development for some years to come. Moreover, according to Assembly and Packaging committee member, Bill Bottoms, "The roadmap reflects the increasing importance of packaging and off-chip interconnection in the cost and performance of electronic systems."

For additional information on semiconductor packaging, go to www.semiconductor.net/packaging