SAW Provides ECD Copper Overburden Thickness Metrology
Alexander E. Braun, Senior Editor -- Semiconductor International, 2/1/2004

The copper electroplating process's wafer-level and die-level uniformity process directly affects the final post-polish thickness of copper interconnect lines used in advanced ICs. Plating process control requires a complex balance between the plating bath's chemical properties, the plating machine's variable parameters, and the incoming wafer's characteristics. A major challenge that faces those working with copper is the requirement to minimize the amount of copper overburden that is plated onto the wafer, while maintaining a uniform fill of features of highly varying density.
This problem is compounded by the fact that post-plating thickness can greatly depend on the local feature geometry, with some process conditions resulting in excess deposition above narrow-linewidth structures. This can lead to excessive overburden or mounding above such structures, creating uniformity predicaments for CMP. While excessive overburden or mounding can be reduced by modifications to the plating process conditions, optimizing these conditions — while keeping them under control — requires metrology to provide feedback of copper thickness over a variety of wafer structures.
An obstacle to all this lies in the fact that it is not possible to approach this problem using blanket monitor wafers with large-area measurement techniques; for example, four-point probe, because electroplating deposition thickness is critically linked to the linewidth of the local geometry on the wafer. This therefore requires the use of techniques capable of measuring on patterned wafers. This situation is but an example of how the introduction of copper has created new metrology requirements (which were undreamed of for aluminum) due to copper processing's pattern-specific nature.
Currently, AFM profiling is one of the standard procedures with which to measure the relative step heights between different features following copper electroplating, to detect mounding above arrays. However, this technique tends to be slow and does not allow for rapid full-wafer monitoring. Further, it does not provide the actual deposited copper thickness.
Obviously, what is required is a technique that can rapidly and non-destructively measure copper electroplating thickness in a small spot on a patterned wafer. A number of small-spot non-contact metal measurement techniques have been introduced to address interconnect metrology. However, because of the large thickness of the copper layer that must be measured, issues relating to the electroplated copper film grain structure and the presence of an underlying structure, it appears that only the laser-induced surface acoustic wave (SAW) technique performs well for the copper overburden application. The technique appears able to measure thick electroplated copper film more easily than techniques based on laser picosecond acoustics, laser thermal profiling, or X-ray fluorescence.
Philips Advanced Metrology Systems (Philips AMS, Natick, Mass.) has developed metrology techniques for rapid measurement of copper overburden thickness using its SurfaceWave metrology tools. According to the company, it has demonstrated this capability for a major Japanese chipmaker, with several wafers prepared by the chipmaker using a variety of plating conditions. Measurements of overburden were made on line arrays of 0.12 µm linewidth and varying pitch, as well as on the surrounding field dielectric.
On Wafer 1 (Figure ), the overburden thickness increased dramatically above the dense line arrays in a non-uniform manner. This indicated a >2000 Å thickness difference between the various array structures, and a 5000 Å total thickness range between the solid pad and the 50% array. This situation would cause considerable difficulties at CMP. The plating chemistry and current were different for Wafer 2, yielding almost totally uniform plating over the arrays — the critical interconnect structures — and smaller total range between the arrays and the solid pad of only ~2000 Å. Wafer 2 would perform better at CMP.
A more subtle effect, detected on Wafer 1, is that the overburden in the field area is reduced as the adjacent array step height increases, presumably because of depletion of reactant in the plating bath in the vicinity of the high overburden regions above the arrays. While this serves to further magnify uniformity problems, it would be difficult to detect with AFM profiling alone.
For additional information on inspection, measurement and test, go to www.semiconductor.net/imt
