3-D Packaging for Wireless Applications

If you were inclined to open a new feature-laden 2.5G cell phone handset and compare it to an earlier "send and receive" handset, some startling differences would become apparent. Circuit boards inside the 2.5G handset certainly have fewer, more tightly laid out, trimmer looking or specialty packages. What cannot be seen, without destroying the handset, is that some packages contain active ICs stacked at least three high. A stacked package in the 2.5G handset could possibly contain a logic chip with two kinds of memory.
 
Handset manufacturers are accomplishing much of the increase in cell phone functionality with 3-D packaging. Overall, they have achieved advances in handset size, weight and cost reduction by dramatically increasing the ratio of silicon area to the associated package area. Market data show that cellular communications products are increasingly the driving force behind the adoption of innovative 3-D package solutions. For these consumer products, individually packaged SRAM or flash memory is no longer sufficient to support the growing list of product features, particularly increases in voice and data functions in cell phones. One market research group shows that, by 2005, stacked-die chip-scale packages will account for more than 80% of the worldwide handset memory market.

Although handsets are the leading consumer product for this technology, 3-D packaging has also worked its way into PDAs, Bluetooth components, memory cards and other products. Successful 3-D packaging has come through both evolutionary and revolutionary advances in core wafer-level and singulated package assembly technologies. These include more delicate wafer thinning, film-based alternatives to paste adhesives for die stacking, and low-loop and long-wire wire bonding. Each IC packaging operation must develop these assembly technologies with robust and cost-effective manufacturing techniques.

Assembling multiple active die vertically inside a single package requires more advanced technologies than those used for single-die assembly. Assembly issues that directly affect manufacturing yield and package reliability include:

• What die thickness is appropriate for the die stack.
• How to stack same-size die.
• How to control wire-loop height.
• What materials work best.
• What substrate technology is best.

Properly stacking die is crucial to the whole process. The die-stack sequence and position dictate use of two- or four-layer substrate routing. Routing complexity also drives substrate selection and affects substrate cost. A die-stack sequence can create limitations to wire-loop height and wire crossing. These wire-bond decisions affect subsequent molding and the extent of wire sweep during encapsulation.

One primary decision is: Can an upper die be rotated 90°? If so, the die can be stacked using a standard die-stacking process. If it cannot, the die must be stacked on top of a spacer. Considerations in die rotation include its impact on package size and trace routing, and the impact of either on overall cost.

The chosen die-stack order dictates a choice between conventional nonconductive epoxy (NCE) or film adhesive (FA) technologies. In general, NCE has a lower cost and involves a minimal capital investment because it is done with existing die bonders. The weaknesses of NCE processing, however, include control of epoxy voids, fillet coverage, epoxy bond-line thickness control and die tilt — all critical issues for successful die stacking. In addition, resin bleed can contaminate die-bond pads and make wire bonding difficult. There is also a risk of passivation damage caused by silica and alumina filler content in NCE when it is compressed and cured at die attach.

Assemblers may need to develop FA technology to address process concerns associated with using NCE in die-stacking applications. Because resin bleed is a major concern when stacked die are the same size, FA is the only workable option. In addition, FA provides a uniform bond-line thickness that is void-free with 100% edge coverage. A 50 µm clearance between bond pads on a lower die and the upper die edge has been demonstrated. FA also acts as a stress absorber between die. FA technology requires an initial capital investment into wafer-back lamination and die-bonder modifications, and involves higher materials cost. However, the increasingly higher demand for die-stacking applications can offset these additional expenses.

1. Elastomer inter-die spacers (not visible between die) provide the needed bondable gap between die in this stack of four active die.

Stacking same- or similar-size die requires use of inter-die spacers that provide a wire-bondable gap so wires do not touch die edges (Fig. 1 ). A spacer can be a blank silicon chip (i.e., not an active die) or an elastomer spacer. The use of spacers affects mold-cap thickness and total package height. Choosing a reasonable spacing gap is important for mold compound flow. Turbulent mold-compound flow inside a mold cavity is anticipated from the structure of multiple die.

Process capability for controlling wire-loop height and mold flow dictates the spacer gap. A larger mold gap works against the trend to thinner package height where the goal might be 1.0-1.2 mm high packages with four functional chips.

Thinning die to <100 µm is paramount for stacks with three or more die. Developing suitable die thinning technology requires consideration of several issues. Thinning wafers creates stress from silicon-grain deformation induced during wafer backgrinding. This can lead to die cracking and wafer handling problems (i.e., warped wafers). The solution requires a fine polishing step to control warpage (e.g., results average 4.65 µm, 1σ=1.83) and surface roughness (e.g., 0.0184 µm, 1σ=0.0057) using either dry plasma or wet etching, or mechanical super polishing.

Wire bonding is the dominant factor influencing die-stack height and package profile in stacked-die applications. Assembly engineers must address management of wire length while using low wire loops, without affecting assembly yield and package quality. Several wire-bond technologies are available. Selection factors include top die surface-to-mold clearance and the distance between bond pads and die edges.

When the gap is sufficient (i.e., >0.3 mm) to allow for wire-trajectory loops, conventional ball bonding gives the highest productivity and bonding quality. More specifically, this condition reduces the chance of ball-neck damage. For a gap <0.3 mm, alternatives to ball bonding include (Fig. 2 ):

• Standoff stitch bonding (SSB) bonds first to the substrate's bond finger and second to a gold stud (previously applied with a separate wire bonding operation) on the chip's bond pad. SSB enables <100 µm loops without damaging bonding wires.
• Gold wedge bonding can produce <75 µm loops and longer wire spans compared with conventional ball bonding, making it applicable for enhanced die stack-up in very low-profile packages.
• Ultralow-loop bonding can achieve wire loops <75 µm without ball neck damage by using current ball bonding technology with a different wire trajectory tool. This method enables equipment productivity and long wire spans that are similar to conventional ball bonding.

2. Low-loop wire-bonding technologies offer alternatives to ball bonding. From left to right: SSB, gold wedge, and ultralow.

Wire-bonding characterization is particularly crucial when an upper die in a stack is larger or overhangs a lower die; a bond capillary can induce a cushioning movement or vibration that results in a weak bond. Although design conventions would typically put a larger die below a smaller die, there are situations where larger die need to be on top because of substrate routing or because overhangs occur when stacked die are only similar in size. In these cases, it has been found that ball bonding is superior to SSB because SSB requires more force. In fact, stacked-die packages have been processed with 3 mil thick die with 25 mil die overhang, passing standard temperature cycling tests without wire-bond process issues as verified by wire-pull and ball-shear tests.

The benefits of stacked-die packaging can include lower total package and system cost, shortened development time and faster time-to-market. Stacked-die packaging also allows for mixed IC fabrication and device technologies (i.e., different die types and sizes) combined in the same footprint. While stacked-die applications will increase from our current capability to stack three and four active die, to stacking five or more active die, some limitations will dictate the seemingly natural evolution to package stacking for some applications (e.g., a stackable extremely thin CSP, etCSP, Fig. 3 ).

3. Package stacking is a better solution for some applications, since package test prior to stacking can prevent die yield loss. Amkor’s stackable etCSP, side and top views.

For some applications, particularly when stacking increasingly diverse combinations of logic and memory, the limitations of stacked-die packaging can involve logistics and controlling die cost, or yield and quality concerns, including known good die. Where applicable, package stacking must be considered as an option to die stacking because burn-in and test are available before stacking, therefore reducing die yield loss. Package stacking also gives a system manufacturer more direct control over its procurement of die from multiple, competitive chipmakers.

When 3.0G cell phone handsets become available, look inside for the latest technology in stacked packages.