Faster Qualification Through Proactive Risk Assessment

There is a new approach to reliability qualification that reduces the time to qualify a new product while improving engineering resource allocation. Infineon Technologies (Munich, Germany) has proven the capability of its physics-of-failure (PoF) concept in several pilot projects.

Traditional approaches for qualification use product stress testing under defined conditions with the intension of simulating field conditions at an accelerated level in order to stimulate failure modes that would likely occur during use. Though these methods have proven very successful, chip complexity has increased, making stress testing more complicated, and time-consuming root cause analysis a common culprit in time-to-market delays.

Infineon's Andreas Preussger and colleagues presented the PoF qualification approach, which they applied to a Smart Power technology, at the recent IEEE International Reliability Physics Symposium . The approach uses a risk and opportunity assessment process (Figure ) to systematically compare necessary requirements to the ability to fulfill them. Differences are opportunities that can be exploited or risks that must be minimized. The process involves:

1. A product tree analysis
2. Gathering requirements
3. Gathering present abilities for realizing target values
4. Risk and opportunity assessment
5. Advanced quality planning and qualification

The process includes a deductive approach (view from outside in) that looks at the transformation of requirements by product and process properties, while the inductive approach (view from inside out) looks at potential faults in the product/processes and their effects. (Source: Infineon Technologies)

In this example, the product tree separated into the package and chip on the first level. Then the second level divides the chip into device and interconnect; then NMOS, PMOS, etc.; the interconnect into contact, metal 1, via 1, etc.; and the package into leadframe, solder, wirebond, etc.

For reliability and processability, the requirements are conditions of operation and time in application, respectively, and the processing conditions at the OEM. In step 2, the user examines the stress levels (load) that causes degradation of an element, at what intensity and for what period of time.

Step 3 examines the present abilities for achieving target values for the element parameters over the operating range and the process capability. Typically, this capability is known from specifications (electrical parameters or design rules) from an existing qualified process. If not, in-depth testing and simulation must be performed.

Next, risk levels of unacceptable, high, medium, low or unknown are assigned to the target vs. ability. Qualification resources are relegated to high- and medium-risk topics to minimize the samples needed for stress testing.

In step 5, a so-called We Know Matrix (WKM) is constructed in the project planning stages and updated throughout development. It is divided into sections of information gathering (requirements, influencing elements and present abilities); risk and opportunity assessment; and definition of measures (for prevention improvement qualification and opportunity exploitation).

In the smart power example, digital and analog circuits are monolithically integrated with power switches, based on a 0.5 µm CMOS technology. There is a new requirement for guaranteed performance up to 175°C (from 150°C previously) and longer lifetime (5000 hr). An analog NMOS transistor is one of the relevant elements, and the stability of its analog drain current at the specified operation point is the corresponding parameter in the matrix. The level of risk was assigned to various stressors and the actual reliability at the loads was measured. Risk levels are assigned with respect to the customer (function, application and reliability), the organization (manufacturability, yield, cost, liability), society (environment, safety, legality) and overall.

In response to a high risk for high-temperature gate stress, the group took measures to improve the process, and they reviewed the specifications for the analog transistors together with product development, and reassessed the real operating conditions and needs in the circuits. This led to a reassessment of the maximum allowed voltage for the analog applications. The WKM reflects all these changes throughout qualification, and this information helps when qualifying other products at higher temperatures. When all risk levels reach low, the qualification is complete.

For additional information on yield management, go to www.semiconductor.net/yield