Time Travel to 2029: Nanotechnology Thrives

"Future generations may well judge our success — and our wisdom — by how well we realize the potential of nano while avoiding the pitfalls."—Joseph Bordogna, Deputy Director of the U.S. National Science Foundation, plenary session at 2003 IEDM.
 
Looking into the future 25 years is perhaps a task better suited to soothsayers than scientists and industry professionals. However, given the rate of technology innovation that the semiconductor industry is undergoing presently, it would come as no surprise if device manufacturers continued on the pace of rapid technology developments in design, manufacturing technology and new packaging implementation. Moore's Law of smaller, faster, cheaper devices will persist, but with strong consideration for the needs for reduced power consumption and better heat dissipation. "The power problem," as it has been called, will require equally innovative solutions to those of pushing faster clock speed on microprocessors and increasing storage capability in memory devices.

A concept called ambient intelligence (Fig. 1 ), where technology is embedded in our natural surroundings, ever present and available for access by the individual, will be accomplished within the next 25 years. What is unclear is the way it will be implemented, and whether certain products will prove feasible and affordable such as paper-like displays and small sensors embedded in paint that might facilitate communication in houses and hotels.

A combination of key capabilities will be needed to bring nanotechnology and ambient intelligence into the mainstream about two decades from now — in design, design-for-manufacturing, materials synthesis using, for instance, self assembly, development of new interconnect approaches such as carbon nanotubes, and 3-D interconnect and 3-D packaging alternatives. Nanotechnology not only requires interaction among the circuit, chip and system designers and manufacturers, but also cross-pollination of disciplines among biological, chemical, mechanical and electrical functions, which is already occurring today.

1. Ambient intelligence is the vision that technology will become invisible, embedded in our surrounding environment, ever available for use by, and adapted to, the user. Key to the fulfillment of ambient intelligence is low-cost wireless networks, ubiquitous sensor networks, low-cost and low-power chips, and convenient human/machine interfaces.

Nanotechnology is expected to permeate most aspects of everyday life, from the ways that heart conditions are monitored to the way parents check up on their children. "Nanotechnology is not an epiphany of an entirely new technology. It's an evolution of processes and concepts that we've used for years to make semiconductors," explained Larry Thompson, CEO of the New Jersey Nanotechnology Consortium (Murray Hill, N.J.). Nanostructures and nanodevices, which will typically perform some electronic functions, are perhaps the most critical subset of nanotechnology, which essentially involves the manipulation of materials at the atomic level. Figure 2 highlights the explosive growth of nanoelectronic types, from NEMS and optoelectronics to sensors used in biological applications. These fields will grow between now and 2029, and new types of nanosystems are likely to be developed as well.

"We've only begun to see how ubiquitous silicon can and will become a part of our lives," said Chris Mack, vice president of lithography technology at KLA-Tencor (San Jose). "What has happened, and I think continues to happen, is that our technology is racing ahead so fast that the applications just aren't keeping up."

The sizzling pace of technology and potential production devices five to 10 years out can be gleaned from the latest IEDM conference, where researchers presented advanced ways to engineer substrates to combine various materials, ways to manufacture 3-D structures such as FinFETs to improve performance, or increase device speed using strained silicon.

2. Twenty-five years from now, people may look back to the 50 years preceding the present as a steadily evolving industry that suddenly exploded in a big bang of device types around the turn of the 21st century. (Source: IMEC)

Aside from such seemingly mainstream developments, there were reports on more eccentric devices such as electronic cloth, silicon transistors on plastic substrates, artificial skin, nanowires and spintronics.¹

"It was a particularly exciting conference this year with many windows of possibilities related to downscaling, performance and tearing down many of the 'red brick walls' in the roadmap," commented Ivo Raaijmakers, director of R&D and CTO of front-end operations for ASM International (Bilthoven, Netherlands).

Scientists will continue to bring down the red brick walls, up to some fundamental limits, when, even then, creative new materials, architectures or designs will allow some type of extendibility in performance.

There are several examples of where this has already occurred, as in the addition of immersion lithography to the roadmap this year, which is possibly within two years of production realization. To the casual observer, immersion technology arrived very suddenly, but due to the feasibility and low cost of implementation, the programs are going forward for 193 nm lithography.

Strained silicon technology jumped ahead several generations — originally expected for the 32 nm node, Intel has indicated it is already using strained silicon at the 90 nm node. The speed improvement was enabled by a strained channel, which increases hole and electron mobility in addition to scaling of the channel length.

Strained silicon is particularly attractive because it does not affect design rules. "Some of these technology decisions, whether to use SOI, strained silicon, high-k dielectrics, people are working on all three, but at some moment they make the decision of how and when to implement, based on what gives the biggest return at the lowest risk," said Chris Werkhoven, vice president of strategic marketing at ASM America (Phoenix). Now that some companies have managed the introduction of a few new materials in the fab, particularly high-k dielectrics and copper, which both required changes in mindset, future material transitions will face a lower threshold, he said. The engineers' uncanny ability to find or create technology solutions to seemingly unmovable barriers is becoming more the status quo for the industry, which is expected to continue.

Architects of the 2003 ITRS assigned risk levels to the various device types in logic, memory and non-classical CMOS devices (Fig. 3 ). At the same time, the industry remains conservative in adopting wholly new architectures until all paths to extendibility are exhausted. For example, planar CMOS structures have not yet reached their limit of performance. Like optical lithography, the call for its demise has always been premature.

3. There is increasing risk associated with all changes in device architecture and expanding CMOS-based FETs to their performance limit before implementing non-classical CMOS alternatives. (Source: 2003 ITRS)

Extendibility by any means possible will continue to preclude tool and infrastructure changes. "Through sophisticated integration, for instance, of litho and testing and software, not only do we get the next generation of devices, but the cycle time and time to manufacturing and time to concept are reduced, which is equally important to figuring out what the next generation of litho equipment will be," said Richard Aurelio, chairman and CEO of Varian Semiconductor Equipment Associates Inc. (VSEA, Gloucester, Mass.).

Ambient intelligence refers to a natural environment with hidden technology rather than the electronic "boxes" that consumers have grown accustomed to. In order to have fully behind-the-scenes functionality, the human/machine interface must be very simple, and the technology must be available at all times. High-end automobiles already have much of this intelligence, with air bags that are released during a crash and automatic headlights.

In the areas of healthcare and medicine, a sea change is expected due to the aging population and the computing and networking capabilities available today. Many of the functions that were previously only performed in hospitals or medical offices will be moving to the home or may be performed in a mobile environment. Nanotechnology is also playing a critical role in drug discovery, drug administration and diagnostics.

"Ambient intelligence will be a must 25 years from now," said Ludo Deferm, vice president of business development at IMEC (Leuven, Belgium). "To make these products, we need to combine a lot of things. People in medicine have to work with electrical engineers, chip designers, computer engineers, systems designers, software, etc., to make sure that these complex systems with large digital chips can perform the needs of the application."

The second big area of ambient intelligence requires a distributed network of sensors, many of which will be body-area network (BAN) sensors, which will wirelessly communicate with distributed electronic systems. Wireless technology is also pushing for the development of a variety of low-power chips and MEMS that can perform one specific function.

The human interface with devices is, in turn, influencing packaging. Rather than an electrode or plastic package with pins, one future package may be more like a patch, which monitors a function such as temperature, blood pressure, etc., signaling a designated electronic system when values exceed acceptable limits.

For portable applications, the consumer also desires the elimination of batteries in most of these applications, which will give rise to devices called energy scavengers. Energy scavengers use motion or temperature differential to generate low levels of power. "So the system has to use less power and scavenging capability has to be increased, and these two will meet somewhere to work the systems that use substantially less power than they do now," Deferm said.

Lack of user-friendliness is a common complaint regarding technology, particularly when the user has to adapt to the device rather than the other way around. For ambient intelligence to become a working reality, increasingly complex electronic appliances such as televisions and personal computers must be made more user-friendly so that their full functionality can be realized.

A key driver for friendlier user interfaces is the increasing demand for personal productivity in modern society, and the need to make better use of limited time available both at work and away. Voice recognition is only the first step toward smarter systems that can act as a personal assistant. These cognitive systems are under development, which will help the user in decision-making. Smart computers or systems that are capable of adapting to the profile of the user and take action in response to a limited set of commands will help efficiency and task management. According to Deferm, these expert systems require an enormous amount of system engineering.

What is keeping the industry from realizing this dream of smart machines? On this point, opinions differ, and perhaps there are several reasons. Deferm claims that the primary focus has been on functionality, and that designers are now becoming more acutely aware of the need for simpler interaction between people and systems. KLA-Tencor's Mack said, "Today, design in all of its aspects is the primary limiter to growth in the semiconductor industry. The technology has outpaced our ability to design products that take full advantage of that technology. So it's part of a bigger design gap."

Others argue that, because so much of the future of the microelectronics industry will rely on consumer purchases, the market pull on the part of the user is more dominant today than the market push of smaller, faster, cheaper chips, which largely drove the industry to date. Many chips are now developed for the consumer from the start, so optimization for the man/machine interface is a more straightforward requirement than it was in the past. For instance, GPS systems were originally developed for military applications; they were later refined for navigation in cars.

A third possibility is that so much specialization occurs in engineering these days that there are few forums where system-level, circuit, materials and device experts get together to solve the bigger problems. However, organization such as IMEC, Albany Nanotech (Albany, N.Y.) and Microelectronics Advanced Research Corp. (MARCO, Research Triangle Park, N.C.) are pursuing many viable solutions at the research level.

The high cost of wafer fabs and IC manufacturing is forcing companies to make wiser decisions regarding product mix and risk management. At the same time, the industry is undergoing massive change, including substantial new materials adoption and the first use of alternative transistor structures (Fig. 4 ).

4. To continue following Moore’s Law, a number of material changes, architecture changes and lithography advances will be needed within a short period of time. (Source: IMEC)

The changes to copper interconnects and low/ultralow-k dielectrics will extend current interconnect approaches only so far before more radical changes will be needed such as carbon nanotubes and/or new architectures. John Kelly, senior director of R&D at Novellus Systems (San Jose) gives the example that "the optic nerve is a terahertz communications link that operates very differently from computers today. It is possible that completely new approaches will be needed in the future." He attributes the idea to Fortes and Harris, researchers at the University of Florida who are working on a delay-based interconnect structure.

Carbon nanotubes represent the most promising alternative because they have ballistic conduction, so minimal resistance or RC delay. One of the principle difficulties in using carbon nanotubes to build electronic devices lies in manipulating them controllably. Scientists are even looking to DNA molecules as a method of connecting a number of nanotubes via a DNA scaffold.²

Carl Thompson, professor of materials science and engineering at the Massachusetts Institute of Technology (MIT, Cambridge, Mass.), explained that a variety of conducting and semiconducting nanotubes could be fabricated; the bandgap of the material depends on the way the tube is twisted. Though the industry is unclear on whether nanowires will act as a blanket replacement for copper interconnects, many other applications are possible for nanotubes. "One place that ordered arrays of nanostructures will almost certainly be useful is sensor arrays of all kinds," Thompson said.

Thompson's group is also engineering cooling techniques for 3-D interconnects. "Between 2-D interconnects and 3-D interconnects, the power dissipation issues get considerably worse," he said. "We are working on building microchannels through 3-D circuits, between pairs of device layers so that the tubes in the plane of the device can be used for cooling, similar to techniques used in heat pipes."

Thompson further describes what he calls a renaissance in the materials field, where computational material science allows design and simulation of new materials, with intended properties, well before the material is synthesized in the lab. "I think this will have an effect on all fields of electronics," he said.

In the interim, it is likely that device manufacturers will continue to optimize interconnect design and materials. One novel approach, X Architecture, involves pervasive use of diagonal wiring to shorten interconnect length. X Architecture reduces wire length by up to 20%, and eliminates 30% of the vias, according to Aki Fujimura, X Initiative steering group member and CTO of Cadence Design Systems (San Jose). The X Initiative is a group of 39 companies developing design technology, masks and manufacturing processes for X Architecture.

"Vias are contributing quite significantly right now to the failure rates of chips, so the fewer vias you have, the greater chance your chip is working," Fujimura said.

Fujimura thinks that collaborative programs, such as the X Initiative, will be the only way to solve the industry's technical challenges in the future. "One of the things that is changing right now and is making chips fail, is that design people do the best they can, mask people do the best they can, and wafer manufacturers do the best they can — but these independent efforts are no longer sufficient. Much more collaboration is required from the beginning," he said.

Finally, system-in-package (SiP), 3-D packaging, and even the stacking of systems (Fig. 5 ) look promising as ways to continue to decrease the effect of interconnect delay on system performance. Wafer thinning and bonding capabilities have reached production worthiness, and will eventually allow the combination of an infinite number of materials, starting with SOI and SiGe, but also silicon with different crystalline orientations. Such novel material combinations will enable many new applications for semiconductor, MEMS, MOEMS and 3-D packaging realization.³

5. A generic 3-D SiP system can integrate SiPs on each level in a small cube (1 mm to several centimeters). Each layer can perform a different overall task, and be fully tested before assembly. (Source: IMEC)

Lithography as bottleneck

Throughout the industry's history, lithography's ability to pattern smaller and smaller features has been both the enabling technology and a potential bottleneck. To date, optical lithography has not limited progress due to the ability to use resolution enhancement to pattern features smaller than the wavelength used in the exposure tool. But with CD control requirements approaching a single nanometer, it appears that a fundamental limit may be on the horizon.

"We will not be able to extend optical lithography to its ultimate limit unless we do everything right on the design side," Mack said. He commented that, while design-for-manufacturing (DFM) is a favorite marketing term of EDA companies, there is no doubt that manufacturability must be taken into account when laying out the chips, and the DFM gap will have an increasing influence on future scaling capability.