Innovation Drives Packaging, Fab Integration

Historically, wafer fabs have viewed packaging semiconductor devices as an afterthought, a production bottleneck and a backward operation characterized by manual or batch processes, albeit a necessary evil. Meanwhile, the front end has excelled at reducing device dimensions and cost, yet many question how much further miniaturization can be achieved and at what cost. In recent times, the semiconductor industry has arrived at a more integrated approach to fab and packaging activities that emphasizes greater cooperation and pooling of resources. Smaller features, higher R&D costs for capital equipment and technology processes, and faster time-to-market pressures with shorter product lifetimes all conspire to compel practical solutions for today's streamlined business models.

As semiconductor packaging emerges first from the industry's prolonged slump, it appears that back-end technology breakthroughs are leading many integration efforts. Post-passivation layer (PPL) technologies, wafer bumping, wafer-level packaging, advanced flip-chip and 3-D/stacked packages serve as primary examples.

Well beyond traditional passivation functions of protecting circuit surfaces from contaminants and moisture, PPL technologies add thin-film dielectric and sputtered or plated metal layers on top of the chip to enhance device functionality and serve as buffers for fragile IC layers. These additional layers often include redistribution lines (RDLs) for I/O rerouting, and also expand the possibilities for passives integration at the chip/package interface. In either instance, greater performance is achieved as integration takes place at the package level and the form factor shrinks.

Although cutting-edge PPL technologies and infrastructure are limited, wafer bumping has already evolved into a service business. Typically, solder bumps are placed on an IC and form the interconnection with the package. At the wafer level, an underbump metallurgy (UBM) — variously gold, gold stud bump, electroless nickel and gold, or solder — is placed on the I/O pad to provide a barrier against electromigration before a reflow process forms the solderable material into spheres. Later, depending on desired pitch, these bumped wafers can be used to form flip-chips, chip-scale packages (CSPs), ball grid arrays (BGAs), or other package types.

Wafer-level packaging (WLP) attempts to reverse the process of dicing first then packaging in order to leverage economies of scale through labor savings while maintaining high yields. Instead of single-die packaging, WLP focuses on redistributing IC pad pitches, and packaging and testing the entire wafer. This approach yields a smaller chip size and packages without internal wire bonds, thereby boosting performance. After singulation, the package-to-board assembly resembles conventional flip-chip assembly processes.

Flip-chip technology itself has seen recent advances. At the same time, unit volumes have been spiking as the installed equipment base and mature processes become more widespread. Although the flip-chip's improved performance, increased functionality, higher reliability and thermal advantages have been proven for some time, the associated additional assembly costs and lack of industry infrastructure prevented widespread market penetration sooner. Today, the availability of low-cost bumped die, better underfill materials with improved dispensing techniques, and market demand for smaller portable devices with advanced features justify flip-chip technology.

Perhaps the most visible example of fab and packaging innovation through integration is the stacked or 3-D package. Largely enabled by front-end wafer thinning technologies (which made them manufacturable), and driven by smaller and faster portable devices, 3-D packages offer higher performance at reduced cost. Moreover, packaging that exploits the vertical dimension may offer a convenient bypass to Moore's Law by offering better performance and functionality outside conventional semiconductor design rule shrinks. Within a given area, 3-D packaging employs the same number of interconnections at the board level; all additional interconnections are inter-package wire bonds inside the multiple die or multiple package stacked construction.

Clearly, many advanced packaging innovations have borrowed heavily from wafer fab technologies. Processes such as lithography, sputtering, electroplating, back grinding, passivation, redistribution and etching all routinely occur in packaging houses and serve to blur the lines between the separate ends of the semiconductor manufacturing spectrum. Further, new materials developments such as low-k dielectrics, copper and polymers find equal application and interaction on wafers and in packages.

In many instances, front- and back-end operations have already stopped viewing themselves as separate entities and have adopted a more holistic vision. Closer interaction and collaboration will undoubtedly produce a more integrated industry approach characterized by mutual equipment development and infrastructure, joint process development and a highly coordinated technology handoff of wafers to packaging houses.

For additional information on semiconductor packaging, go to www.semiconductor.net/packaging