New Roadmap Identifies Industry Challenges

A newly revised International Technology Roadmap for Semiconductors (ITRS) was released last month, providing an updated reference of requirements, potential solutions, and their timing for the semiconductor industry. The 2003 ITRS represents a full revision of all the tables, as well as a revision of the text. This new edition extends to the year 2018.

The 2003 ITRS does not predict a further acceleration in the timing of introduction of new technologies as the industry struggles through the worst recession of its history.

As a way of monitoring internode progress, the new ITRS includes an "hp" designation, referring to the half-pitch dimensions of the first level of metal lines (hp90 nm, for example, will be introduced in 2004). These dimensions are used because they are quite clear during patterning and processing. "We are providing another dimension to what we consider technology nodes," said International SEMATECH's Linda Wilson, managing editor/information manager, ITRS. "The ITRS uses the Metal 1 half-pitch for DRAM that typically, so far, has been the smallest feature size that we can track easily." This move should help clarify the confusion about what it means to have achieved success at a certain technology node.

New in the 2003 ITRS is a substantially updated Emerging Research Devices section, which includes non-classical CMOS devices. In addition, analysis of potential post-CMOS devices has been substantially expanded to include considerations on alternate logic-state-variable nanoscale devices. This paves the way to a complete technological revolution looming ahead toward the end of the next decade. The technology needs of wireless applications are also included in a new section. And, for the first time, a relative comparison of the ultimate performance of silicon devices and the performance of devices produced by using other semiconductors is introduced into the ITRS. "We've expanded the emerging research devices to add necessary detail to potential devices beyond CMOS and non-classical CMOS devices as well the III-V architectures," Wilson said.

The ITRS includes an overview of major technological issues, identified as "Grand Challenges." The challenges are classified into two categories: Enhancing Performance and Cost-Effective Manufacturing . They are also described according to the near-term (2003-2009) and the long-term (2010-2018) timeframes of the roadmap (Table 1 ). The following near-term challenges are excerpted from the ITRS. The full ITRS is available at http://public.itrs.net.

Performance and power dissipation in high-performance applications. Aggressive scaling of the gate length in high-performance applications makes device parameter optimization quite difficult. Ultrashallow junction formation for suppressing the short-channel effect cannot be achieved without incurring a significant increase of parasitic resistance. Doping requires quite precise profile design and process control, whereas increasing channel doping concentration degrades carrier mobility, lowering the drain current. Moreover, statistical fluctuation of channel dopants causes increasing variation of the threshold voltage, posing difficulty in circuit design while scaling the supply voltage. Gate insulator, on the other hand, becomes thinner and thinner because of the requirement for rapid CV/I improvement. Excessive gate leakage current caused by excessively thin oxynitride films will necessitate the introduction of high-k material circa 2007. Introduction of various technology innovations ("technology boosters"), such as strained silicon, metal gate, ultrathin body SOI MOSFETs, and multiple-gate MOSFETs including FinFETs, should also be considered to meet the drain current requirement and to control short-channel effects with scaling. The solutions for these issues should be pursued concurrently with circuit design and architecture improvements, particularly to manage power dissipation.

Performance and leakage in low-power applications. In low-power applications (mainly portable products), suppression of the leakage current is strictly required in low standby power (LSTP) applications, whereas maximization of device performance under low supply voltage becomes more important in low operating power (LOP) applications. In both LSTP and LOP applications, the gate leakage of oxynitride films will soon reach an unacceptable level, driving introduction of high-k materials as early as 2006. In LSTP applications, very slow scaling of the supply voltage makes overall device optimization difficult. Introduction of "technology boosters" should also be considered, and power management using circuit design and architecture techniques becomes important.

New gate stack processes and materials. Continued reduction of the gate length accompanies approximately proportional reduction of the gate oxide thickness in the region where tunneling leakage current becomes dominant. In microprocessor applications, for example, gate physical thickness could reach 1 nm as early as 2006. Although extension of oxynitride to <1 nm may be consistent with the device reliability requirement for microprocessors, it will no longer meet the strict leakage current requirement in LSTP applications. Therefore, introduction of a higher-k material in which tunneling current can be suppressed while maintaining the drain current will be necessary in LSTP applications first (circa 2006), followed by microprocessor applications (circa 2007). In either case, the gate electrode material and process should be optimized so that the depletion width in the gate electrode may be minimized and the boron diffusion prevented. The former necessitates the introduction of metal gates having appropriate work function after the conventional polysilicon ceases to work. These material changes pose a great challenge in MOSFET technology, where SiO₂/poly-Si has long played a central role as the most reliable gate stack system.

CMOS integration of new memory materials and processes. Continued DRAM scaling requires construction of memory capacitors in ever smaller cell areas, while maintaining the memory capacitance of 25-35 fF to ensure reliability of stored data. This has resulted in the introduction of high-k materials, such as aluminum oxide, aluminates (e.g., HfAlO_x) and tantalum oxide, along with a 3-D memory structure. The capacitor structures are shifting from metal-insulator-silicon (MIS) to metal-insulator-metal (MIM) to avoid problems associated with capacitor dielectric thickness. For further scaling, however, it will be necessary to address process construction by using a thinner dielectric film and/or a higher-k material. In flash memory devices, on the other hand, continuous scaling and the reduction in write voltage requires the use of a thinner inter-poly and tunnel oxide, suggesting the need to introduce high-k material into flash memory processes. Along with scaling issues of the ferroelectric material in FeRAM, process integration of these materials will continue to pose major challenges in the development of memory applications.

Optical and post-optical mask fabrication. Accuracy and fabrication cost of optical masks continue to be major concerns in lithography. To realize aggressively scaled microprocessor gate length, gate electrode formation utilizes post-etch in addition to resist slimming. Since part of linewidth tolerance (CD control) in the completed gate electrode is shared by the etch process, the margin in the lithography process is reduced. Moreover, utilization of low-k₁ processes enhances the mask error factor (MEF), resulting in the requirement for more stringent accuracy in mask writing. Thus, it is becoming hard for the current mask writer to meet the accuracy required by the roadmap. Increasing difficulty in inspections (e.g., optical proximity correction), rising machine cost of drawing, and lowering mask yield with aggressive scaling raises the mask cost greatly. Regarding mask technology in next-generation lithography (NGL), it is not yet clear how to construct pellicles and defect-free masks.

Introduction of new materials to meet conductivity and dielectric permittivity. To minimize the interconnect delay, development of low-k materials together with low-resistivity metal systems is critical. Low-k materials should have sufficient mechanical integrity to survive harsh integration processes, such as chemical mechanical planarization (CMP), etching, and assembly/packaging. Since resistivity of narrow-lined copper interconnect is predicted to start to increase below 100 nm linewidth because of electron scattering at the copper barrier-metal interface, care should be taken for intermediate wiring at the hp65 nm node (circa 2007). "Barrier engineering," including construction of very thin and low-resistivity barrier metal, as well as efficient "pore shield" for low-k materials, is essential to achieve high reliability of interconnect systems.

Engineering manufacturable interconnect structures. Introduction of new materials and technologies for interconnect has raised additional issues due to their combinations and interactions. These include adhesion at the interfaces, contamination, diffusion and leakage concerns. Mechanical damage by CMP has significantly retarded implementation of low-k materials. Complexity in interconnect structure also makes the effective dielectric constant deviate from its intrinsic value. Failure mechanisms in the copper/low-k systems should be clarified, along with establishment of detection metrology and predictive models. With regard to assembly and packaging technology, lack of optimization tools for interconnect/packaging architecture design makes total optimization of interconnect systems difficult.

Power management. Even off-currents in low-power devices increase by a factor of 10 per node, so design technology must maintain constant static power. On the other hand, while power dissipation for high-performance microprocessors will exceed package limits by 25× in 15 years, design technology must achieve power limits. As a result, efficient power management requires highly complex controllability across the entire LSI. Additionally, any power optimization must simultaneously and fully exploit varying degrees of freedom, for example, by switching the operating power state of circuits using multi-V_t, multi-T_ox, multi-V_dd in the LSI core block, while guiding the architecture, operating system and software.

High-frequency circuit modeling for 5-40 GHz applications. Accurate and efficient modeling of interconnect parasitics and delays is of prime importance. 2-D and 3-D effects on interconnects must be considered with their statistical variations. Partitioning is needed for distributed R-C-L extractions. Efficient simulation techniques should handle multilayer dielectrics. Compact models for active devices are needed for, for example, HBTs, CMOS and LDMOSTs. These include non-quasi-static effects and surrounding parasitics. Compact models for passive devices are needed for, for example, varactors, inductors, high-density capacitors, transformers and transmission lines. The parameter extraction for RF compact models preferably tries to minimize RF measurements. Parameters should be extracted from standard I-V and C-V measurements with supporting simulations, if needed. Third harmonic distortion for 40 GHz applications implies modeling of harmonics up to 120 GHz. Modeling of effects that have a more global influence gains in importance. Examples are crosstalk, substrate return path, substrate coupling, EM radiation, and heating. For these global effects, accurate and efficient (layout) extraction techniques are needed. If possible, models should be physics-based to enable efficient modeling of statistics and variations.

Front-end process modeling for nanometer structures. Front-end process modeling for nanometer structures is the key challenge for the prediction of result from device fabrication. It overlaps to some extent with the difficult challenge, "Ultimate nanoscale CMOS simulation capability," which, however, also includes materials and device simulation. Most important and challenging in the area of front-end process modeling is the modeling of ultrashallow junction formation, which starts from very low-energy implant and especially focuses on the thermal annealing and diffusion of dopants. Because of the strongly reduced thermal budgets needed for shallow junctions, that process is highly transient and is governed by the diffusion and reaction of dopant atoms and defects, and especially by the dynamics of clusters of these two. Implantation damage, amorphization, recrystallization, and silicidation must be accurately simulated. In view of the need to increase carrier mobilities in the channel, the modeling of stress and strain and their influence on diffusion and activation has become vital, especially for strained silicon, SiGe, and for SOI structures. Model development, calibration and evaluation, as well as process characterization, require numerous experimental activities and large progress in the metrology for dopants, defects and stress, especially regarding 2-D and 3-D measurements.

Failure analysis and diagnosis. Enhanced automated software diagnostic capabilities are required to improve physical failure analysis return on investment. Characterization capabilities must identify, locate and distinguish individual defect types. And accuracy and throughput must be improved. For example, throughput is expected to increase from days to hours. Failure analysis methods for analog devices constitute another critical issue. DFT is essential to localize failures because it can improve efficiency by reducing design complexities associated with testing. Defect types and behavior will continue to evolve with advances in fabrication process technology, so existing and novel fault models will require fundamental research to address emerging defects.

Tool and R&D cost. Lithography has long accounted for a significant portion of overall semiconductor manufacturing costs, and this situation will become more marked. Shortening of the source wavelength obliged us to use a new and costly lens material, CaF₂. The combination of lengthening R&D periods and shorter technology lifetimes is also pushing up the cost of lithography tools. On the other hand, possible extension of optical lithography down to the hp45 nm node with the use of immersion technology will make the requirement for mask accuracy significantly difficult. Moreover, existence of multiple candidates for lithography tools in future generations leads to fragmentation of development resources. All these factors are predicted to significantly degrade ROI of lithography in future generations.

Responding to rapidly changing complex business requirements. To correspond to customers' rapidly changing complex business requirements, various types of business models, such as IDM, fabless, foundry, joint venture, and outsourcing, have emerged and become widespread. Factories now must integrate an even larger number of new and different items of equipment and software applications in a much shorter time while realizing high process reliability and volume productivity, which poses great challenges in factory integration. Construction of information exchange/control systems covering all the relevant fields, extending from design, mask, FEOL and BEOL to testing, packaging, etc., is crucial. The ability to model factory performance using various metrics is essential for optimizing the production output. Also, the achievement of higher visibility in manufacturing processes is important to find solutions that meet the increasing expectations of customers.

Meeting process requirements at hp65 and hp45 nm nodes. How to construct a manufacturing system that guarantees product reliability at the hp65 and hp45 nm nodes is not clear. With reduced process windows and increasingly difficult targets, process control will becomes quite difficult in many process modules. Integration of NGL into a factory leads to unwieldy complexity in the factory design. A novel streamlined system that controls various parameters for stabilizing fabrication processes and achieving satisfactory product quality, while realizing shortening of the cycle time of products, should be pursued.

Tools and methodologies to address chip and package co-design. Assembly and packaging have become critical, and thus are factors influencing the competitiveness of LSI technology, because they have significant effects on operating frequency, power consumption, complexity, form factor, reliability and cost of final products. Concurrent design at both the chip and package levels is essential to satisfy stringent requirements for the system, including design cycle time. To do this, establishment of simulation tools and methodologies that can accurately predict electrical characteristics, thermal dissipation and thermo-mechanical stress, while considering physical layout, cost and environmental impact, is required.

Chemical and material assessments. The rapid introduction of new chemicals/materials/processes requires new rapid assessment methodologies to ensure that new chemicals/materials can be used in manufacturing without inducing new hazardous impacts on human health, safety and the environment. Although methodologies are needed to meet the evaluation and quantification demands for ESH impacts, the focus is currently on expediting process implementation.

Design for manufacture and test, and systematic yield. IC designs must be optimized for a given process capability and must be testable and diagnosable. Understanding systematic mechanism-limited yield (SMLY) is mandatory for achieving historic yield ramps in the future. Design to process compatibility, design for manufacturability, design for test, and design for diagnosability would be perfected through SMLY model development.

High-aspect-ratio inspection. Control of high-aspect-ratio technologies such as damascene challenges all metrology methods. Key requirements are void detection in copper lines and pore size distribution in patterned low-k materials. The need is to have a rapid, inline observation of a very small number of voids/larger pores. CD measurements are also required for very high-aspect-ratio structures that are made from porous dielectric materials, and require 3-D information for trench and via/contact sidewalls. These measurements will be further complicated by the underlying multi-film complexity. The detection of via defects near/at the bottom of a damascene trench will also continue to be a grand challenge. However, the challenge is complicated by the simultaneous need for high sensitivity and high throughput. High-speed, cost-effective detection tools that satisfy both demands are therefore needed.

Non-visual defect sourcing, and manufacture- and test-oriented design. Fault isolation complexity is expected to grow exponentially, combining the difficult tasks of defining fault dimensions in the horizontal plane and vertical layers. It is especially difficult to analyze circuit failures that leave no detectable physical remnant. Accordingly, new analysis tools and techniques that can isolate those non-visual failures are needed. Although IC current design is optimized for a given process capability and is testable/diagnosable, many defects that cause electrical faults are still not detectable inline. Tools are needed that enable design and process matching so that optimum yields can be achieved.

Factory-level and company-wide metrology integration. Real-time, in situ, integrated and inline metrology is required for manufacturing complicated devices. Continued development of robust sensors, process controllers, and data management will allow integration of add-on sensors. Standards for process controllers and data management must be agreed upon. Massive quantities of raw data should be converted to information useful for enhancing the yield of a semiconductor manufacturing process. Better sensors must be developed for trench etch end point, ion species/energy/dosage (current), and wafer temperature during rapid thermal annealing.

Starting materials manufacturing metrology. The introduction of new substrates such as SOI affects impurity detection (especially particles) at levels of interest and edge exclusion for metrology tools. In particular, CD, film thickness and defect detection are influenced by thin SOI optical properties, and charging by electron and ion beams. SiGe and strained silicon layers add to the complexity of this challenge. Existing capabilities will not meet roadmap specifications. Very small particles must be detected and properly sized. Capabilities for SOI wafers, SiGe and strained silicon need enhancement. Challenges originate from the extra optical reflection in SOI and the surface.

The Grand Challenges were excerpted from the ITRS Executive Summary. Copyright: Semiconductor Industry Association. The International Technology Roadmap for Semiconductors, 2003 edition. International SEMATECH: Austin, Texas, 2003.