Polycrystalline XRD Method Finds Metal Defects

Most advanced device processing materials fall into one of three ordering states of atoms: single-crystal, polycrystalline and amorphous. Both barrier and interconnect-via metals generally fit in the polycrystalline category. Fab monitoring of these metals is limited mostly to resistivity, thickness and microscopy. The challenge has been not only to identify critical flaws in the barrier-metal layers when they occur, but also to quickly isolate their cause and develop closed-loop control techniques for the metallization process to avoid such defects in first place.

Depending on process conditions, the crystalline phase of tantalum and TaN liners can vary significantly. Crystallographic texture — crystallite orientation — of the barrier and copper fill also exhibits far greater variability than observed in previous aluminum generations. Although qualitative offline X-ray diffraction (XRD) analysis has shown a clear connection between phase-texture and critical process yield parameters such as electromigration, stress migration, resistivity, defect count and adhesion, no one has yet translated this analysis into a fab-level method for yield enhancement. Both the absolute values and in-wafer uniformity of phase-texture are important in the process control environment.

HyperNex Inc. (State College, Pa.) has pursued the development of a quantitative XRD metrology system specifically for fab-level monitoring of polycrystalline phase and texture. In 2001, HyperNex began joint work with a U.S. semiconductor company to develop the technique specifically for copper processing. The result is a fab system that uses an area detector combined with proprietary wafer motion protocols and XRD analysis algorithms. This combination provides for rapid quantitative phase and texture analysis down to spot sizes as small as 26 × 35 µm.

The top images correlate the volume fraction of the Cu(111) orientation from a 49-point map to yield of via opens on a 300 mm wafer. Four more 49-point maps (bottom) show that increasing N2 flow rate during TaNx deposition increases the α-Ta/β-Ta ratio of the tantalum overlayer. (Source: HyperNex)

Phase mapping of the α-Ta/β-Ta ratio is an example of quantitative output making use of integrated peak intensities corrected for the actual measured texture, which can adversely affect the intensity. For quantitative crystallographic texture, the system generates the orientation distribution function (ODF) from which a single numeric value, the volume fraction (V_f) of a particular crystallographic orientation, can be output — for example, V_fCu(111).

Process wafers run through the system have demonstrated that yield loss, poor parametrics, and poor electromigration strongly correlate with the distribution of the tantalum phase, orientation and thickness, and copper orientation. It should also be noted that, thought resistivity maps can determine the presence of α- or β-Ta prior to copper seed deposition, the distribution in resistivity values does not always correlate to the volume fraction of the tantalum phases or their across-wafer distribution. The XRD system provides a relatively fast and simple way to accurately determine whether process changes can modulate the microstructure to maximize yield and reliability.

The HyperNex technique does have some limitations, however. Even at the smallest current X-ray beam size, the system is limited to controlled test structures such as parallel line sets. In the case of very small low-density feature sizes, measurement times can increase to ~120 sec per point compared with 10-30 sec for monitor wafers.

On the other hand, a traditional XRD system might require several hours to perform an equivalent measurement, and be capable of providing only a qualitative result. X-rays will also readily penetrate multiple layers, so structures are generally limited to one layer in a controlled location, such as within the scribe line. Despite these limitations, the technique offers an innovative opportunity for fabs to optimize performance and yield on product wafer, based on fundamental microstructure properties.

For additional information on inspection, measurement and test, go to www.semiconductor.net/imt