Single-Electron Transistors: The Ultimate in Scaling?

In the not too distant future, conventional CMOS technology is likely to reach its limits. At that point, CMOS transistors will have only about 100 electrons at any given time underneath the gate. Some scientists are looking at ways to take that to the extreme to have only one electron beneath the gate. Behold the single-electron transistor (SET). "In about 10-15 years, it will be the end of CMOS scaling as we know it," said Christoph Wasshuber of Texas Instruments (TI, Dallas). "We'll have to do something different if we want to continue Moore's Law and continue to shrink these devices and make them cheaper and faster with lower power and so on. At that point, SET could come in and not really replace CMOS, but combine with it to further extend the roadmap."

Wasshuber said that, if you look at all the other nanodevices that have been proposed, single-electron devices are furthest ahead, not just conceptually but because of their potential to be easily combined with CMOS. "We can really transition from a purely CMOS technology to something where we start to see a few SET devices, maybe for memory," he said. "At the end, there may be just a few CMOS devices to interface with the real world, with SET devices making up the majority of the components on your chip."

TI, working in conjunction with the Swiss Federal Institute of Technology (Lausanne, Switzerland), has described a potential way to use SETs to perform logic functions and dramatically reduce the size and power consumption of future semiconductor devices. In a paper presented at the International Electron Devices Meeting (IEDM) last month, the researchers showed (through simulation only) that a combination of SETs and standard CMOS transistors can provide enough gain and current drive to perform logic functions at a much smaller scale than will eventually be possible with CMOS alone. SETs can potentially take the industry all the way to the theoretical limit of electrons for computing applications by allowing the use of a single electron to represent a logic state.

Simulations presented at IEDM showed very encouraging results and address random background charges — an obstacle that had effectively stopped major research on SETs — by using a modulation technique that takes advantage of the periodic current voltage characteristic of SETs. "Using this variable-gate SET, you can show that such a gate is immune to random background charges for certain characteristics," Wasshuber said. "The conceptual barrier is gone. You can now start thinking of using hundreds of thousands and millions of these SETs working together in a logic circuit doing some useful work."

In addition to being very small, SETs can be used as more than an on-off switch as are most CMOS transistors. "The I-V characteristic of an SET is fundamentally different than the characteristic of the MOSFET; it is a periodic function. I would need dozens of MOSFETs to replicate the periodic function that I have in one single SET," Wasshuber said. "Besides being able to shrink an SET much further to essentially atomistic dimensions if you want, which you can't do with a MOSFET, you have an additional, denser functionality that will allow you even further shrinking and power consumption reduction."

The basic structure of an SET is a quantum dot, measuring ~1-10 nm, with three leads. One is a source lead, another is a drain lead. This enables electrons to tunnel from the source lead to the quantum dot, and then from the quantum dot to the drain. The third lead is a gate electrode that is capacitively coupled to influence the potential of the quantum dot. In the work at IEDM, the researchers described a tunable-gate SET device fabricated with a suspended conductive layer and a nano-air gap on the order of some tenths of a nanometer (Figure ). This proposed gate — which couples electrical and mechanical characteristics at the nanoscale — could be used to design high-density neural networks or a dense array of analog-to-digital flash converters, which demand high-speed operation with low power consumption.

This advanced design of a single-electron transistor (SET) device employs a movable electrode that is actuated by an applied electrostatic force between the gate and a fixed electrode (n+) biased by VG2. A rather highgate surface (>10 mm2), a small airgap (<100 nm) and a low stiffness gate(<1 N/m) are required for low-voltage actuation. (Source: Texas Instruments)

The next challenge for researchers is to reliably manufacture many SETs in a CMOS-compatible process on silicon. The first application for SETs could be for memory and special applications in metrology, such as primary thermometers and super sensitive electrometers.

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