Reliability: The Big Hurdle in High-k Gate Dielectrics

Though high-k gate dielectrics demonstrate some of the same breakdown behavior as SiO₂-based dielectrics, certain mechanisms, such as charge trapping, occur much more readily in high-k devices. When a fixed charge density forms at the polysilicon/high-k interfaces, it typically accelerates negative bias temperature instability (NBTI) degradation and often leads to shifts in threshold voltage and flatband voltage.

Much of the focus of current work is on testing high-k/poly and high-k/metal gate structures (see "How to Electrically Qualify High-k Gates ," Semiconductor International, October 2003). There is also much research designed to understand the breakdown behavior and the causes of well-known phenomena of mobility degradation and Fermi-level pinning associated with high-k dielectrics.

At the recent IEEE International Electron Devices Meeting (IEDM), some of the industry's finest researchers closely examined the reliability characteristics of high-k gate dielectrics with both polysilicon and metal gates.

For instance, Zhibin Ren and coworkers at IBM (Hopewell Junction and Yorktown Heights, N.Y.) identified a scattering mechanism that fundamentally limits the mobility of a high-k material. They propose that some carrier mobility degradation is caused by scattering with low-energy optical phonons (soft phonons) associated with the highly polarizable bonds in the high-k material. Though there are other causes of mobility degradation such as Coulomb scattering, which may be reduced or eliminated through process optimization, the phonon scattering represents an intrinsic degradation mechanism. The IBM researchers presented compelling theoretic and experimental evidence that the inversion channel mobility in HfO₂/SiO(N)/Si is significantly reduced by soft-phonon scattering. They suggest that there is a necessary trade-off between mobility degradation and gate leakage improvements.

Ajit Shanware and others at Texas Instruments (Dallas), together with researchers from International SEMATECH (Austin, Texas), compared charge trapping behavior in HfSiON to HfO₂ gate dielectrics using DC and pulsed I_D-V_G characterization. The DC measurements showed there was a V_t shift for HfO₂ films, but no shifts were observed for HfSiON. Constant voltage stress measurements showed that the threshold voltage shift in HfO₂ is 10× greater than that in HfSiON. They attribute HfSiON's better electrical stability to its significantly lower number of traps and lower trap cross section compared with HfO₂. In addition, pulsed I_D-V_G measurements showed greater hysterisis for NFETs using HfO₂ and poly gate relative to HfO₂ and TiN gate. There was also greater loss in drive current with the HfO₂/poly devices relative to HfO₂/TiN devices.

Katsuyuki Sekine and coworkers from Toshiba Corp. (Kanagawa, Japan) compared plasma nitridation to thermal nitridation techniques for nitrogen incorporation in HfSiO gate dielectrics. They demonstrated that plasma nitridation, with >15 atom% nitrogen, leads to thinner equivalent oxide thickness, lower gate leakage current, higher channel mobility and higher thermal stability. The group used a conventional CMOS process (Figure), with dopant activation anneal at 1000°C. Using MOCVD on a hydrogen-terminated silicon substrate, MOCVD of Hf/(Hf+Si)=0.5 was deposited. Plasma nitridation was performed in Ar/N₂ ambient while the thermal process was performed in NH₃, with the subsequent anneal in O₂.

The researchers determined that the thermal process was more likely to damage the quality of the interface between the silicon and high-k dielectric, which negatively impacts mobility and shifts the flatband voltage. Thermal nitridation also increases the thickness of the interfacial layer because the nitrogen is reacting with the silicon surface as well as the HfSiO film.

In another process optimization example, researchers from Samsung (Kyunggi-Do, Korea) determined that an ozone pretreatment improves the NBTI and electrical characteristics of HfAlON gate dielectric. They performed two types of anneals after the 300°C ALD of HfO₂-Al₂O₃ laminate: a 950°C RTA in N₂ and an in situ three-step nitridation in NH₃, reoxidation in O₂, and N₂ anneal. The ozone pretreatment effectively removed hydrogen, nitrogen and water impurities on the silicon surface prior to ALD, thereby improving NBTI characteristics. However, the positive bias temperature instability (PBTI) characteristics were negatively impacted when arsenic and phosphorus dopants from the polysilicon gate penetrated the high-k film. When TaN gates were used instead, PBTI characteristics were not degraded. The researchers propose further optimization of the gate stack for improved reliability.

For additional information on yield management, go to www.semiconductor.net/yield