Qualifying Packages at 260°C

Pre-Y2K, most commercial electronic components had been designed and qualified to typical reflow temperatures of 183-200°C (the eutectic temperature of PbSn alloys). However, the performance standard for the new millennium is 260°C. When presented the probability that an additional 60°C would be required to guarantee performance, product and packaging teams became distressed. Justifiably so, cost managers were also reluctant to move forward until there was solid indication that the lead-free movement was real. Would there be enough time to successfully transition, maintain competitive advantages, and not incur large cost expenditures?
 
Evaluating the current material sets (mold compound, die attach, lead finish, etc.) to determine performance at 260°C is the primary task for package assemblers. Regardless of package type, the top two issues are increased intermetallic (IMC) growth and reduced moisture sensitivity level (MSL) performance. Visually "degraded" mold compound and laminates have been noted, but the suppliers indicate the material would meet datasheet specifications.

Typical data have suggested MSL drops by two levels of sensitivity with chip-scale packages (CSPs). Modules and small-profile thin quad flat packages (TQFPs) suffer the most (several have been registered at MSL level 3 or 4 prior to lead-free evaluation), with drops in MSL. At level 3, manufacturing flows can be created to assure usage prior to elapsing out-of-bag-limits. Shifts in MSL add cost to both supplier and customer. A higher MSL also provides an opportunity for IMC growth.

Higher MSLs reduce out-of-bag time limits and increase the likelihood material will require a baking process. Baking contributes to IMC growth and standard ball shear tests on CSP and BGA packages after bake confirm drops in shear strength (and missing balls). More control has to be placed at various stages in the assembly process, particularly on the gold layers, to guarantee reliability.

Preliminary DOE results help predict the best choice for replacement solder paste. With no drop-in replacements available, the material of choice will need a similar melting temperature to SnPb, have resistance to gold IMC formation, and be economical, safe and readily available. The SnCu and SnCuAg alloys melt near 220°C and are slightly less expensive than other alloys. Having readily available constituents with none as harmful as lead, the solder joints age well in reliability testing, and SnCuAg readily alloys with traditional SnPb and most of the alternative lead-free solders and finishes.

The silver constituent in SnAgCu solders helps prevent the dissolution of gold into solder joints. This is important because gold is used as a barrier layer in lead finishes, multilayer laminates and PCBs. Excessive gold in contact with tin or lead causes the formation of detrimental IMCs, which in turn lead to shifts in circuit impedance, reduce the bond strength of solder joints, and contribute to crack formation. Gold/gold IMCs can also migrate away from the barrier interface, exposing underlying metals to conditions favoring additional IMC formation.

Packages incorporating gold, such as CSPs and BGAs, modules and NiPdAu-plated leads, are at higher risk to gold IMC formation. Since IMCs can alter time-zero impedance, the shifts in electrical (and mechanical) properties can impact performance and reduce reliability. Because of the higher impedance values, high-frequency RF devices may be particularly vulnerable to variation during processing and over the lifetime of a device. In search for a root cause, an inexperienced product or reliability engineer may incorrectly identify the IC die as the problem, leading to needless project delays and cost overruns.

1. Cross section of a BGA package.

IMCs begin to grow at moderately low temperatures (~125°C) and hasten at slightly higher temperatures (~150°C). Packages may be repeatedly subjected to such temperature ranges at burn-in, MSL baking, test, and during SMT reflow. CSP/BGA package performance can be especially susceptible to IMC issues as a gold barrier layer is in direct contact with solder balls. Interfacial cracks, balls falling off the package, reduced ball shear, and parametric and functional shifts in device performance are common pareto items. Figure 1 is a cross section of a BGA package for reference. Figure 2 shows a crack after 4 hours at 125°C, followed by 4 hours at 150°C. At reflow, higher temperatures will be encountered that can lead to time-zero problems as well.

2. Solder ball with a crack at the interface (4 hr @ 125°C, followed by 4 hr @ 150°C).

Most "pre" lead-free material sets (mold compounds, die attach materials, laminates, etc.) were not designed to withstand 260°C temperature profiles. Drops in MSL performance of one to three levels are common. The replacement material sets cannot guarantee the original MSL. PCB assemblers unaccustomed to levels of 2a (Table ) or higher have to implement practices to ensure components do not exceed out-of-bag limits and forecast expenditures for additional process equipment to support component bake processes.

IMC formation and MSL degradation are but two issues to consider when designing packages. Either has the potential to negate the advantages of the best silicon die, yield improvement strategies and cost saving efforts. Reliability teams must specify the correct qualification tests to expose risks to conclude if designs support short-term, intermediate and long-term performance criteria.

Lead-free qualification strategies require aggressive reliability goals to ensure packages exceed minimum customer requirements. As lead-free dominates corporate roadmaps, choosing the correct qualification tests is necessary, as well as discerning if data can be extracted using qualification by similarity (QBS). It requires parallel study on lead-free material sets (mold compounds, die attach materials, laminates, etc.), as well as detailing studies on metal-to-metal interactions. Temperature cycling (TC) and thermal shock (TS) present an opportunity to discuss the merits of QBS.

3. BGA interface layer after 24 hr @ 125°C.

A net time saving is gained using TS in lieu of both TS and TC to qualify traditional SnPb solders. Decades of performance and operational data allow the reliability manager an opportunity to omit TC, thus shaving weeks out of project cycle time in favor of the shorter TS. Figure 3 shows a view of a BGA interface after 24 hours at 125°C. But TC should not be excluded for lead-free material sets because it provides a necessary tool to evaluate long-term solder joint reliability and IMC growth rate.

The cumulative time spent near 150°C during TC better simulates the growth of IMCs, while TS better evaluates sudden changes in thermomechanical behavior (such as coefficients of expansion). Evaluation of IMC formation in lead-free alloy systems requires the detailed analysis it took decades of work with SnPb material sets to accomplish. To support new reliability decisions, various process and assembly capability data are needed.

For example, some data already confirm the growth of IMCs at the solder ball to socket interface.¹ SnPb solder balls in contact with gold-plated contacts result in 10% of the contacts contaminated with solder material and corresponding damage to some of the solder balls after only 9 hours at 125°C. Likewise, 100% of the contacts were contaminated and all the balls were damaged after 24 hours at 150°C. These results suggest how easily failures could be generated as a result of poorly devised qualification tests.

Consider CSP or BGA ball size as a variable. The area of ball contact to pad will be proportional to D², while the volume is proportional to D³ (A=πD² and volume=1/6πD³). Figure 4 illustrates how a change in ball size from 0.3 to 0.6 mm (±0.05 mm tolerance) results in a 7× change in contact area at the bond interface, impacting shear strength, void acceptance, etc. The same ball size change also dictates an 18× change in solder ball volume and mass, impacting IMC formation, strength and void allowances. Reviewing the SnAu phase diagram, a paltry 4% gold (to tin) differential can affect formation of the detrimental AuSn₄ intermetallic. Plating process variation, poorly toleranced metal layers, or even a small change in solder ball diameter could easily lead to long-term reliability and financial risks if full qualification is not conducted.

4. Visual comparison of solder balls at 0.3 and 0.6 mm

Understanding the interactions of new lead-free material sets will play an important role in product qualification and development. As the semiconductor industry continues to develop new package designs (and qualify old designs) in this state of transition, understanding SnPb and lead-free material interactions will be necessary to improve on-time delivery, support process improvement efforts and sustain implementation of yield enhancement techniques.

There are some variables to consider as semiconductor manufacturers formulate strategies to transition to lead-free material sets. Projecting the impact on intermediate and long-term reliability, qualification should reflect conditions that simulate real-world conditions such as repeat baking, burn-in, multiple reflow, etc., and the impact on MSL and IMC growth.

A time will come when lead-free material sets are as thoroughly understood as SnPb solders. Until then, having access to experienced materials engineers could be the difference between competitive advantage, customer satisfaction and financial loss.