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Industry Reaches Design-for-Manufacturing Crossroads at 130 nm

Laura Peters, Senior Editor -- Semiconductor International, 11/1/2003

While the effects of new materials and subwavelength lithography at the 130 nm node were expected to impact yield more significantly than in past device generations, few people knew that yields would be as poor as they have been. In addition to dealing with new failure mechanisms and other process-induced yield hits, at advanced technology nodes, yield is impacted by the design content. As a result, the industry has reached a crossroads where it can no longer avoid the path called design-for-manufacturing (DFM). Once considered just a fancy acronym for marketers and advertising agents, it is now a necessity for achieving acceptable yields.

Consequently, some of the companies that made their names in yield improvement are extending their reach into the design arena. For example, PDF Solutions (San Jose) recently introduced a process-design software environment that can be used to optimize products for manufacturability before tape-out and before the reticles have been manufactured. "If you do the manufacturability analysis post-reticle, you end up re-spinning the reticle or tweaking the process back to the design, which a foundry will do for a high-volume product, but is not willing to do it for most of their designs," said Michael Buehler-Garcia, vice president of marketing at PDF Solutions. For this reason, the company's pDfx program mainly targets fabless companies rather than IDMs.

The program is based on PDF's experience in deep submicron yield ramping engagements with more than 20 clients worldwide. By simulating nanometer-scale product and process interactions, the company is able to improve the manufacturability of processes, speed yield ramps and time-to-market. The pDfx program, used in conjunction with EDA software from Synopsys, Cadence and Magma, is comprised of software and modified IP library cells that perform yield trade-off analysis during synthesis (Figure ). The yield models have been modeled above the standard cells and logic blocks, the die areas that have the largest impact on yield. The extended IP kit is an extended set of standard cells that have been modified to consider different scenarios of process maturity. "The yield model also considers things that are beyond a standard cell level," Buehler-Garcia explained. "For example, printability not only considers the standard cells, which may be designed to yield perfectly, but also the way the designer has grouped the cells for four or five different types of standard cells."

The DFM environment allows designers to optimize products for manufacturability before tape-out, based on manufacturing risk factors that consider such trade-offs as performance, power and area. (Source: PDF Solutions)

The pDfx software creates a design enhanced for manufacturability based on process knowledge, which can be compared with the initial design to give a possible yield improvement (the estimator module). Then the optimizer module gives the designer the ability to make product-specific trade-offs among such design constraints as performance, power and area. "It lets the designer step through his constraints, and optimize through different manufacturing risk factors," Bueler-Garcia said.

Riko Radojcic, director of business development for design-based yield improvement at PDF, added, "We designed our extended IP elements so that you can optimize for process window, for maximum yield with a mature process, or for minimum variability in performance, and sometimes these parameters can be optimized simultaneously, but often they cannot. So the program allows the designer to choose the most important criteria."

"One of the most important aspects of this program is that it does not change the constraints of the design or the die size, only the placement of the cells," Bueler-Garcia said. Through increment engineering change orders the software places and replaces cells, feeds the information back to the design physical compiler to make sure placement and timing rules have not been violated, then performs another incremental re-optimization with a re-mapped database until the target yield goals are reached. Some of the types of changes might include making cells bigger, moving cells away from the edges of gates, or doubling up of vias where reliability is a concern.

"By definition, any design-for-manufacturing approach has to comprehend the characteristics of a future process, because you are designing today something you will build a year from now," Radojcic said. Because of these ongoing changes, the database used in pDfx had to be upgradeable and expandable, so PDF chose the OpenAccess database.

Use of the software involves license and royalty fees. The license fee is paid upfront, allowing designers to evaluate the trade-offs and determine the possible yield improvement using pDfx with their EDA software. If they choose to run the wafers, they pay a royalty fee at that time.

For additional information on yield management, go to www.semiconductor.net/yield

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