New Transistor Uses 80% Less Power

IBM unveiled the world's first thin-silicon SiGe bipolar transistor on SOI (silicon on insulator). The new device is said to improve performance fourfold or reduce power consumption fivefold in wireless devices compared with the state-of-the-art thin-silicon bipolar technology. Traditional SiGe bipolar transistors cannot be built on thin SOI wafers, which are desirable for CMOS devices. Until now, no one had been able to find a technique to combine CMOS and SiGe bipolar onto one wafer that would maximize the performance of both.

In operation (Figure ), electrons come down from the polysilicon emitter, accelerate through the SiGe base, and make a turn in the SOI layer toward the collector contact electrode. With zero or low voltage applied to the SOI wafer, the current path in the SOI is long, which results in low electric field in the SOI and makes the device suitable for high-voltage applications (pink arrow); with high positive voltage applied to the SOI wafer, the collector contact is virtually extended all the way to the back of the SOI layer under the emitter. The current path is thus shorter (green arrow), making the device suitable for high-speed applications.

IBM said that, as the wireless industry grows, device manufacturers will need better mixed-signal chips that support both computing applications and high-frequency communications applications. SiGe bipolar chips provide RF communications and analog functions, and chipmakers have created SiGe BiCMOS chips that put computing and communications transistors onto one chip instead of using separate chips for computing and communications applications. "As the wireless industry continues to grow, new devices will require greater functionalities, performance and reliability from their components," said T.C. Chen, vice president of science and technology for IBM Research. "The new chip design could be implemented within five years, enabling applications such as video streaming on cell phones."

IBM’s bipolar transistor with silicon-germanium base built on CMOS-compatible SOI wafer. (Source: IBM)

IBM presented details of this new chip design at the 2003 Bipolar/BiCMOS Circuits and Technology Meeting in Toulouse, France. This project was a collaboration between researchers and developers at the IBM Semiconductor Research and Development Center, IBM Research and IBM Microelectronics Division.

For additional information on wafer processing, go to www.semiconductor.net/wafer