Wafer-Level Packaging's Promise

In recent years, front-end semiconductor manufacturing has driven down the cost and size of wafer fabrication at a more rapid pace than back-end die packaging operations. As such, we have arrived at a juncture where packaging the silicon adds a disproportionate share of size and cost to the final product. One solution that addresses this situation, wafer-level packaging, has emerged as a technology bridge between the front- and back-end semiconductor worlds.

Wafer-level packaging (WLP) generates interest and activity among semiconductor packagers because a hungry marketplace demands smaller, powerful portable products that justify WLP inside. Moreover, WLP offers a clear scale advantage over the traditional packaging approach of first dicing and then packaging each die individually. As such, it promises a tremendous labor savings and depends on very high yields to be commercially viable. WLP also offers technical advancements such as the smallest available package, better electrical performance due to shorter interconnections, elimination of an underfill process step, and more efficient use of test resources.

Yet many challenges to volume WLP implementation remain. First, the traditional packaging providers will stretch the physical boundaries of existing products. They recognize that packages such as small outline ICs (SOICs), thin small outline packages (TSOPs), quad flat packs (QFPs), plastic leaded chip carriers (PLCCs), etc., cannot support the latest set of small, powerful portable products. Even ball grid arrays (BGAs), chip-scale packages (CSPs), flip-chips (FCs), and other highly advanced package technologies have been challenged. So the packaging community has responded with fervent activity — producing 3-D CSPs and other "stacked" die, multichip packages, system-in-package (SiP), and various worthy innovations to meet the increased demand.

Apart from traditional package innovation, WLP faces considerable materials, assembly, test and infrastructure development challenges of its own. To gain widespread adoption, WLP must provide known good die that are reliable, environmentally protected and compatible with existing industry production equipment just like single-die packaging. In addition, each application must require sufficiently high numbers of I/Os to justify the initial costs associated with new technology introduction for development of equipment and processes.

Who will perform WLP is also open to speculation. Whether wafer fabs, assembly and test houses, electronics manufacturing service providers or partnership combinations, further blurring of business lines in semiconductor manufacturing is sure to arise. Perhaps convergence of wafer fab and die packaging operations will conspire to benefit all players. Already, we have seen that backgrinding wafers for thinning results in multiple die stacks in packages that fit existing X, Y and Z dimension requirements while significantly boosting performance.

In fact, to achieve higher demand for electrical performance, further miniaturization, higher reliability, and thermal and power management at decreasing cost, packaging operations cannot continue to be performed in isolation. Instead, WLP might be one technology that will reach forward to integrate with wafer fabrication technologies while simultaneously reaching backward to accommodate PCB assembly.

Still in its infancy, WLP promises more than it delivers today. Yet continued integration of fab and packaging worlds holds promise of further interaction and automation between chip and package. Also, with commercial applications demanding higher performance in smaller, portable devices, a hungry marketplace is already at hand.

And, much like the early days of semiconductor manufacturing, automating WLP's processes are sure to continue driving down cost while improving yield. This combination of market readiness and automated production has created the opportunity for turning WLP's promise into a reality. Can the technology deliver while the market window remains open?