Taking off the Masks, and Putting on the Gloves

After spending the better part of a week detailing and discussing the finer points of advanced maskmaking — resolution enhancement, cleaning, defects, data preparation — what better way to wind things up than to ponder the unspeakable: A world without masks. In fact, tensions seemed to run a bit high during "Maskless Lithography: Bark or Bite?" — the final session of this year's Photomask Technology conference in Monterey, Calif.

Before the session began, symposium co-chair Wolfgang Staud of Cadence Design Systems Inc. (San Jose) conceded that maskless lithography was a "balancing act." But he also cited some alarming statistics about today's masks: Some 43% of masks get rejected for functional errors, and 61% of all designs require at least one respin.

Though discussions presented the pros and cons of maskless lithography, one of the strongest proponents was Kevin Cummings, director of advanced reticle technology at ASML's Technology Development Center (Tempe, Ariz.)." Key arguments included the amount of money chipmakers could save on skyrocketing mask costs, a potentially high return on investment, and a reduced time to market for designs.

As the complexity of leading-edge mask designs builds, there's no question that the cost of mask sets is getting out of hand. Maskless lithography could save a chipmaker $50,000 per design at the 130 nm node, $1M at 90 nm, and a whopping $4.5M at 65 nm, Cummings said. At the 22 nm node, he projected the cost of a mask set to an "impossible" $9M-$14.4M. "We just can't keep going up this curve." On top of this, mask usage is becoming increasingly inefficient, Cummings noted. About half of the masks used account for only ~1% of the wafers produced. As did Staud, he pointed to the all-too-frequent respin, a costly scenario when a design defect isn't found until sort.

A key argument against maskless lithography has been its low throughput rate. Whether electron-beam or optical, direct-write schemes will never come close to those being reached for standard photolithography techniques. It is for this reason that maskless proponents encourage its use in prototype situations, or for chip applications (primarily ASICs) that would run only a very few wafers on a given mask set. But Cummings argued that, even at a throughput of just 1 wph, the break-even point is reached at as many as 50 wafers per design. However, it is reasonable to expect a maskless lithography tool to achieve a throughput of ~5 wph, which would increase the break-even point to 700 wafers for a $100,000 mask cost.

And now for the pitch: ASML recently announced its joint development with Micronic Laser Systems (Täby, Sweden) of an optical maskless lithography (OML) system. Based on Micronic's spatial light modulator (SLM) technology used on its latest-generation mask writer, the OML tool purportedly will have a break-even point of >1700 wafers at the 65 nm node, according to Cummings.

Marc Levenson, the original inventor of the phase-shift mask, noted that maskless lithography is hardly a new concept, and questioned why it hasn't taken hold sooner. Cummings' answer: "Masks haven't cost $100,000."

But there's a flip side, of course. And when his turn came, Walt Trybula, senior fellow, lithography, at International SEMATECH (Austin, Texas), presented a strong argument against maskless lithography. His presentation centered on the question, "What happens to the mask if maskless lithography happens?" The answer, in part, is that a reduced use of masks will only make the cost of the remaining masks shoot up even higher.

Breaking down the numbers, Trybula noted that ~700,000 masks were made in 2002. About 6000 of those were for the 130 nm node or lower. In a typical 130 nm mask set, about half of the masks are for critical or near-critical layers — the layers where maskless lithography would make the most sense. That brings the total number of masks likely cut out of the year's equation to 3000.

"Why should I worry about 3000 masks out of 700,000?" Trybula asked. He answered his own question with a look at the ASIC industry, which is expected to spend $400M-$500M in 2005-2006 for 7000-10,000 masks a year, and is expected to be a major user of maskless lithography. "That's about $200M not spent to develop the latest generation of masks." The extra cost of learning, therefore, gets put on the remaining masks in the industry, raising mask prices by an average of $7000-$10,000 each. Because of the reduced learning benefit, Trybula added, cycle times also would become longer.

If maskless lithography comes to fruition, the industry will have the opportunity to see if it is a great time and money saver for low-volume designs, or whether it will spell further trouble for already-spiraling mask costs. As symposium co-chair Kurt Kimmel (recently mask strategy program manager at ISMT and now senior manager at Albany NanoTech) put it at the start of the week, "It may sound like the beginning of our end, talking about maskless lithography. Or is it?"

For additional information on lithography, go to www.semiconductor.net/lithography