Dual Gate Control Provides Threshold Voltage Options

Using novel process technology, Motorola researchers have, for the first time, fabricated a vertical MOSFET structure with perfectly aligned independent gates. The control of the thin channel using second gate allows device characteristics such as threshold voltage and sub-threshold swing (SS) to be modulated dynamically.

Such double-gated devices have become known as finFETs, since their structure resembles a shark's fin, as shown in the Figure (they have also been called omega, tri-gate and delta FETs). They are likely to be the successor to traditional planar FETs, which are running into problems with high leakage currents and short-channel effects as they continue to be scaled down to smaller dimensions. It's not clear exactly when finFET-type devices will be required — the development of a successful high-k gate dielectric, for example, might delay their implementation. But Joe Mogab, vice president and director of Motorola's Advanced Products Research and Development Lab (Austin, Texas), said the 45 nm node would be the most likely initial insertion point. "If we find a good high-k solution — and by good I mean one that enables a full range of transistor types, all the way from low power to high performance — that would certainly stave off the insertion of the finFET-type approach simply because this is a paradigm shift in the architecture that requires some changes to be made, not just in the process but in the design world as well."

Motorola’s multiple independent gate field-effect transistor (MIGFET) is a FinFET with two gates. This enables independent biasing and provides the ability to dynamically adjust the threshold voltage. (Source: Motorola)

FinFET devices that have been proposed so far work by adding additional surfaces to control the channel. Motorola's MIGFET (multiple independent gate field-effect transistor) goes a step further by splitting the gate in two. Leo Mathew, engineer, novel devices at Motorola, explained, "What we have done is be able to split the gate and split it by a few tens of nanometers. This gives us the additional advantage of controlling from multiple surfaces, but also controlling using different independent biasing."

Here's how the MIGFET is fabricated: A very thin silicon channel region of ~25 nm width and 100 nm height is formed on an SOI substrate, with a gate oxide of 24.7 Å thermally grown on top. Using a novel process flow, two independent gate regions are formed on either side of this thin silicon fin. The process keeps the structural integrity of the entire channel and gate structures intact. The process allows the two gates to be perfectly self-aligned to each other. The source and drain regions are then implanted and silicided to make contact. Motorola also developed a novel overhanging spacer technology. The overhang spacer extends beyond the channel region and protects the channel region of the fin from being implanted. It also electrically isolates the silicided source drain and independent gates. A copper back-end process has been used to make contact to the two gates, source and drain. The device has been fabricated using conventional process technologies.

Two isolated gates of 100 nm length are formed; these gates have independent contacts and can be biased to control the thin silicon channel region. This is a key aspect of the device, explained Bich-Yen Nguyen, manager, novel devices at Motorola. "Current planar technology requires that you fabricate multiple transistors, each with a different gate oxide thickness and doping to get two different V_ts (threshold voltages). Using the multi-independent gate, you only need one kind of transistor. You can set them up with different V_ts, or you can tie both gates to have better performance of the device." Mogab added, "You can make this device behave like a good low-power device, or you can make it work like a good high-performance device."

A design flow relying on dual- or triple-threshold voltage options can reduce standby leakage by 2× compared with a single V_t design while still meeting circuit performance and density goals.

"Because of the way our process is done," added Mathew, "it allows you to have a regular finFET and the MIGFET in the same process. In places where you don't need these structures, you will add some additional area because of the second gate. But it will actually reduce the complexity because you could do things with less number of transistors than is normally possible."

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