3-D SEM Speeds Engineering Efforts

For years, the ITRS has called for three-dimensional metrology methods. Despite the fact that CMOS transistors and interconnects are planar-based structures, their taper and profiles are having an increasing impact on the yield and reliability of advanced devices. For instance, in shallow trench isolation (Fig. 1 ), sidewall angle is critical to transistor performance. In copper interconnects, via narrowing near a wide copper line can lead to stress voids and reliability failures.

1. Cross-section and 3-D analysis of this STI structure provides profile and feature width at multiple points in the structure. (Source: FEI)

At this time, there is much debate over whether CD-SEM or scatterometry methods will prevail for in-line CD control. In a similar vein, optical and e-beam based methods are competing for validating processes and defining process windows. In the areas of engineering and process development, device cross-section followed by SEM or TEM inspection is becoming increasingly common. However, this process has always been hindered by slow turnaround time and a lack of statistical significance in the data.

However, new system capabilities may be making these limitations concerns of the past as FIB/SEM processes are made more efficient than the laboratory-type predecessors are. FEI Co. (Hillsboro, Ore.) recently introduced a combination ion-beam/SEM tool that can deliver results for 50 design-of-experiments (DOEs) across multiple data points per wafer in the time it takes a fast lab to perform five cross-sections, according to FEI. And, although speed is central to the performance of the CLM-3D DualBeam system, it is the problems it uncovers during process development that justify its purchase. "In beta testing, the tool was able to identify such problems as missing low-k etch stop in some areas of the wafer," said Anantha Sethuraman of FEI. "This finding was surprising, but it was confirmed by TEM and nano EDX measurements."

He cites another case where copper CMP process variability was causing significant yield loss. The CLM-3D system can be used to determine the CMP process dependency on pattern density, measure the thicknesses of hard mask, dielectric and copper layers, and establish a working process window through DOE analysis.

Customers also can use the tool to measure the thickness of nitride remaining after self-aligned contact etch. "In fabs today, this is controlled by running a wafer, taking it out of the chamber, doing a cross-section and manually measuring the nitride remaining," Sethuraman explained. "With this method, the engineer can gather data on different parts of the same feature such as contact angle, profile overall, top CD, bottom CD, all in two minutes, which is a huge time saver in DRAM process development."

Lithography process windows are shrinking, especially as reticle enhancement technologies are used to produce subwavelength features. In these cases, a process window of ±0.04 µm can become ±0.02 µm, according to Sethuraman, due to the conversion of optical proximity correction (OPC) and phase-shift mask (PSM) data from analog to digital format.

The CLM-3D system automatically mills and cross sections at the point of interest, followed by high-resolution SEM imaging. The performance of the system relies on a new electron beam gun with very short working distance to the sample (for higher resolution), a new ion gun and a faster, more precise stage than in previous-generation tools.

FEI's use of the Merlin CAD navigation and Knights yield management software allows users to transfer wafer map bit failure data to the DualBeam system to drive to a specific location and perform a cross-section at the failure analysis spot. Figure 2 shows a case in which the top CD of a via structure was within 3σ specification (10% of CD), but the via bottom demonstrated 33% CD variation across the wafer. The process was clearly out of control but a single top-down CD-SEM measurement would not have identified this problem. "This is the only metrology method for re-entrant features," Sehuraman said.

2. A 30 minute analysis demonstrates a poorly controlled process with via bottom variation of 33% of CD at one point on the wafer relative to 10% of CD (3σ) at the via top. (Source: FEI)

For additional information on yield management, go to www.semiconductor.net/yield.